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| author | Ben Widawsky <ben.widawsky@intel.com> | 2022-02-01 14:06:32 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-02-08 22:57:31 -0800 |
| commit | 06e279e5ebe4f32ffe544ec96a199870319a7315 (patch) | |
| tree | 5589846d835688f9a93f23d6b39c577621128016 /scripts/gdb/linux/proc.py | |
| parent | 4112a08dd3c5ea0a96029f14061f2320826cfd32 (diff) | |
cxl/pci: Cache device DVSEC offset
The PCIe device DVSEC, defined in the CXL 2.0 spec, 8.1.3 is required to
be implemented by CXL 2.0 endpoint devices. In preparation for consuming
this information in a new cxl_mem driver, retrieve the CXL DVSEC
position and warn about the implications of not finding it. Allow for
mailbox operation even if the CXL DVSEC is missing.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/164375309615.513620.7874131241128599893.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'scripts/gdb/linux/proc.py')
0 files changed, 0 insertions, 0 deletions