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authorLeonard Crestez <leonard.crestez@nxp.com>2019-10-16 11:57:37 +0000
committerShawn Guo <shawnguo@kernel.org>2019-10-25 17:03:00 +0800
commitb04383b6a5588906ffd059a6a9f5344a9c6df58a (patch)
treecd4829d3487a4bee55052623e60d916131802b5b /scripts/gdb/linux/timerlist.py
parent8f2d3c1759d19232edf1e9ef43d40a44e31493d6 (diff)
clk: imx8mq: Define gates for pll1/2 fixed dividers
On imx8mq there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate but these gates are not currently defined in the clock tree. Add them between sys1/2_pll_out and the fixed dividers. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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