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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-05-09 17:23:22 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-05-16 10:47:12 +0200 |
| commit | 77899dd2c094fc99413e18264384cc428c23cd23 (patch) | |
| tree | 5357a8ab39e433946a2c87266a9591de8f5179ec /scripts/gdb/linux/utils.py | |
| parent | aa7a6365d03aacd4714ae62630f0262cac82a478 (diff) | |
arm64: dts: renesas: r8a77970: Add secondary CA53 CPU core
Add a device node for the second Cortex-A53 CPU core on the Renesas
R-Car V3M (r8a77970) SoC, and adjust the interrupt delivery masks for
ARM Generic Interrupt Controller and Architectured Timer.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions