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| author | Rui Salvaterra <rsalvaterra@gmail.com> | 2022-04-28 23:57:55 +0100 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2022-05-13 13:27:40 +0200 |
| commit | 80dd27b6c68c7189b865b4b966aa12c77d1adc1e (patch) | |
| tree | 3175beeec61025243441612e4ce79a86c952b567 /scripts/gdb/linux/utils.py | |
| parent | 7d029cc240a012f0259477c905e84f3975d7cf2f (diff) | |
arm64: dts: mt7622: specify the L2 cache topology
On an MT7622 system, the kernel complains of not being able to detect the cache
hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in
order to fix this.
Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
Link: https://lore.kernel.org/r/20220428225755.785153-1-rsalvaterra@gmail.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions