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| author | Xinyun Liu <xinyun.liu@intel.com> | 2018-10-29 14:18:25 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2018-11-12 17:05:39 +0800 |
| commit | def40774f63ad446aaf5c12e2185045979c06c75 (patch) | |
| tree | cbe8b7f6cec5023f90d376e9035a8d49a5dd6176 /scripts/gdb/linux/utils.py | |
| parent | 5e7154ff5e8e21dc9acac4f8dba7533552365374 (diff) | |
drm/i915/gvt: not to touch undefined MOCS registers
Some engines are not available for all Gens. eg, Gen11 introduced
VCS3/VCS4/VECS2, and VCS2 is not supported on some Gen9 machines. So need to
add check before access them.
Signed-off-by: Xinyun Liu <xinyun.liu@intel.com>
Signed-off-by: Yakui Zhao <Yakui.Zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions