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| author | Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> | 2019-10-22 22:30:19 +0530 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2019-11-06 22:37:22 +0530 |
| commit | 7cb1e57544e5d11e3a2742c5acb69562d02af235 (patch) | |
| tree | 634ec38f64e146728dba41f5bc0a6ee5e6705a4a /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 535b4b0c050b79db6a63097599fc87a156db6b2c (diff) | |
dt-bindings: dmaengine: xilinx_dma: Add binding for Xilinx MCDMA IP
Add devicetree binding for Xilinx AXI Multichannel Direct Memory Access
(AXI MCDMA) IP. The AXI MCDMA provides high-bandwidth direct memory
access between memory and AXI4-Stream target peripherals. The AXI MCDMA
core provides a scatter-gather interface with multiple channel support
with independent configuration.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1571763622-29281-4-git-send-email-radhey.shyam.pandey@xilinx.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions