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authorBharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>2016-09-01 15:44:42 +0530
committerBjorn Helgaas <bhelgaas@google.com>2016-09-13 10:38:19 -0500
commit3cd049ab9edd48a41955b8d05f0bc57ead918456 (patch)
tree8c02857a2f569c5a83e97f5626242b8185d97178 /tools/perf/scripts/python/export-to-postgresql.py
parentb584fa1fde71aa57fb63d32f66ff6c192ff7f2c5 (diff)
PCI: xilinx: Clear interrupt register for invalid interrupt
The interrupt decode register is not being cleared if an invalid interrupt arises. Clear the decode register in this case. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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