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authorPooya Keshavarzi <Pooya.Keshavarzi@de.bosch.com>2016-04-19 08:29:55 +0200
committerSimon Horman <horms+renesas@verge.net.au>2016-05-30 09:34:49 +0900
commit457f47b7651ccb1828c1d02f7ace0d07e9b16f33 (patch)
tree1a40be51409c5b358b7a43737852f4b549dda81e /tools/perf/scripts/python/export-to-postgresql.py
parent3cac478cce564c11f56f30bd16530c2757b3e4f3 (diff)
arm64: dts: r8a7795: Increase the size of GIC-400 mapped registers
There are some requirements about the GIC-400 memory layout and its mapping if using 64k aligned base addresses like on r8a7795. See e.g. http://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=21550029f709072aacf3b9 Map the whole memory range instead of only 0x2000. This will fix the issue that some hypervisors, e.g. Xen, fail to handle the interrupts correctly. Signed-off-by: Pooya Keshavarzi <Pooya.Keshavarzi@de.bosch.com> Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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