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| author | Peter Zijlstra <peterz@infradead.org> | 2021-10-22 17:49:53 +0200 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2021-10-22 18:21:28 +0200 |
| commit | 55409ac5c371c6403012d5f4df5e7c6cf0e7dce6 (patch) | |
| tree | f6a18ee9347c902213e3a33d11a73c8ab3d68e2d /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | eaed27d0d01a89a510736d87f10cea02042b4756 (diff) | |
sched,x86: Fix L2 cache mask
Currently AMD/Hygon do not populate l2c_id, this means that for SMT
enabled systems they report an L2 per thread. This is ofcourse not
true but was harmless so far.
However, since commit: 66558b730f25 ("sched: Add cluster scheduler
level for x86") the scheduler topology setup requires:
SMT <= L2 <= LLC
Which leads to noisy warnings and possibly weird behaviour on affected
chips.
Therefore change the topology generation such that if l2c_id is not
populated it follows the SMT topology, thereby satisfying the
constraint.
Fixes: 66558b730f25 ("sched: Add cluster scheduler level for x86")
Reported-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Tom Lendacky <thomas.lendacky@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions