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| author | Jani Nikula <jani.nikula@intel.com> | 2021-10-11 21:21:44 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2021-10-12 12:10:39 +0300 |
| commit | 5c31e9d013b52cc8420ca97e5ae004c9d4b8cf7f (patch) | |
| tree | 758705fbb048e03db8b0fba8d140534b8dcd2516 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 319f4def310cc0851208410e05db325e6c884046 (diff) | |
drm/i915/dg2: update link training for 128b/132b
The 128b/132b channel coding link training uses more straightforward TX
FFE preset values. Reuse voltage tries and max vswing for retry logic.
The delays for 128b/132b are still all wrong, but this is regardless a
step forward.
v2: Fix UHBR rate checks, use intel_dp_is_uhbr() helper
v3:
- Rebase
- Modify intel_dp_adjust_request_changed() and
intel_dp_link_max_vswing_reached() to take 128b/132b into
account. (Ville)
v4:
- Train request printing for TX FFE (Ville)
- Log 8b/10b vs. 128b/132b (Ville)
- Add helper for per-lane max vswing / tx ffe (Ville)
- Name functions with tx_ffe/vswing instead of 128b132b/8b10b
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211011182144.22074-2-jani.nikula@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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