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authorLuca Abeni <luca.abeni@santannapisa.it>2020-05-20 15:42:41 +0200
committerPeter Zijlstra <peterz@infradead.org>2020-06-15 14:10:05 +0200
commit60ffd5edc5e4fa69622c125c54ef8e7d5d894af8 (patch)
tree28335309287723ee841f9713ddd520e17f078f89 /tools/perf/scripts/python/export-to-postgresql.py
parentfc9dc698472aa460a8b3b036d9b1d0b751f12f58 (diff)
sched/deadline: Improve admission control for asymmetric CPU capacities
The current SCHED_DEADLINE (DL) admission control ensures that sum of reserved CPU bandwidth < x * M where x = /proc/sys/kernel/sched_rt_{runtime,period}_us M = # CPUs in root domain. DL admission control works well for homogeneous systems where the capacity of all CPUs are equal (1024). I.e. bounded tardiness for DL and non-starvation of non-DL tasks is guaranteed. But on heterogeneous systems where capacity of CPUs are different it could fail by over-allocating CPU time on smaller capacity CPUs. On an Arm big.LITTLE/DynamIQ system DL tasks can easily starve other tasks making it unusable. Fix this by explicitly considering the CPU capacity in the DL admission test by replacing M with the root domain CPU capacity sum. Signed-off-by: Luca Abeni <luca.abeni@santannapisa.it> Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Juri Lelli <juri.lelli@redhat.com> Link: https://lkml.kernel.org/r/20200520134243.19352-4-dietmar.eggemann@arm.com
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