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| author | Jisheng Zhang <jszhang@marvell.com> | 2016-03-30 19:55:21 +0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2016-03-31 15:15:01 -0400 |
| commit | 9bd9ddb7f89edae241d2da78e3119f226b9b0cf6 (patch) | |
| tree | d276b0b55aaeb9ca6efbefc74c79e0f3fb4f5882 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | b7854efce20be7c7bcd43424dee027124e9af27f (diff) | |
net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES
The mvneta is also used in some Marvell berlin family SoCs which may
have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE
usage with L1_CACHE_BYTES.
And since dma_alloc_coherent() is always cacheline size aligned, so
remove the align checks.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions