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| author | José Roberto de Souza <jose.souza@intel.com> | 2020-06-25 18:01:49 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2020-06-30 17:25:47 -0700 |
| commit | a5523e2ff074a5a44b778f7c6483a882c2c88ecc (patch) | |
| tree | a9f7bc962a9d634e0ba8c6d275deb52a0d161c2a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 19167eb064da81ca7c837ecef61b23921606acd4 (diff) | |
drm/i915: Add PSR2 selective fetch registers
This registers will be used to implement PSR2 manual tracking/selective
fetch.
v2:
- Fixed typo in _PLANE_SEL_FETCH_BASE
- Renamed PSR2_MAN_TRK_CTL bits to better match spec names
- Renamed _PLANE_SEL_FETCH_* to better match spec names
BSpec: 55229
BSpec: 50424
BSpec: 50420
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200626010151.221388-3-jose.souza@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions