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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2021-07-02 14:50:03 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-07-19 10:53:53 +0200 |
| commit | d520af345189c04095bdd256d3601864601ac562 (patch) | |
| tree | 29b382f29d19f261315dc596d26b8791c7525a5a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 03fa6e4b2622035389a4beb9699551d63d130493 (diff) | |
clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries
Add SSIF-2 clock and reset entries in CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210702135010.5937-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions