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authorStephen Boyd <sboyd@codeaurora.org>2017-11-14 10:07:15 -0800
committerStephen Boyd <sboyd@codeaurora.org>2017-11-14 10:07:15 -0800
commit042e2e9c2c8bdd88e30160bfb587f825b0ce5407 (patch)
tree233494a49a76460593b6ae25cefdf56d60796bda /tools/perf/scripts/python/export-to-sqlite.py
parent6705fc944107756857f5f2301f99a9ba7f702a04 (diff)
parent22ef01a203d27fee8b7694020b7e722db7efd2a7 (diff)
Merge tag 'tegra-for-4.15-clk-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
Pull tegra clk drivers updates from Thierry Reding: This contains cleanups and minor fixes for the Tegra clock driver. * tag 'tegra-for-4.15-clk-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init() clk: tegra: dfll: Fix drvdata overwriting issue clk: tegra: Fix cclk_lp divisor register clk: tegra: Bump SCLK clock rate to 216 MHz clk: tegra: Use common definition of APBDMA clock gate clk: tegra: Correct parent of the APBDMA clock clk: tegra: Add AHB DMA clock entry clk: tegra: Mark APB clock as critical clk: tegra: Make tegra_clk_pll_params __ro_after_init clk: tegra: Fix sor1_out clock implementation clk: tegra: Use tegra_clk_register_periph_data() clk: tegra: Add peripheral clock registration helper clk: tegra: Check BPMP response return code dt-bindings: clock: tegra: Add sor1_out clock firmware: tegra: Propagate error code to caller
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