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authorChen-Yu Tsai <wens@csie.org>2018-12-05 18:11:50 +0800
committerMaxime Ripard <maxime.ripard@bootlin.com>2018-12-05 12:08:17 +0100
commit37bb18398aa190c281228e8ac76d892744dc1677 (patch)
treea5ed0736b71cbab9ac04148f4ab23f66d5d40be6 /tools/perf/scripts/python/export-to-sqlite.py
parent64f28430cf152e7e2836df37e51c56e31e3647c2 (diff)
clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL
The audio blocks require specific clock rates. Until now we were using the closest clock rate possible with integer N-M factors. This resulted in audio playback being slightly slower than it should be. The vendor kernel gets around this (for newer SoCs) by using sigma-delta modulation to generate a fractional-N factor. As the PLL hardware is identical in most chips, we can back port the settings from the newer SoC, in this case the H3, onto the A33. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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