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author | Stephen Boyd <sboyd@kernel.org> | 2021-06-21 16:36:46 -0700 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2021-06-21 16:36:46 -0700 |
commit | 3f4e557db50805c5033ee486e7e028ba82e66f1b (patch) | |
tree | ae444eacf681904c6b8ca6494fc85f78831eb08b /tools/perf/scripts/python/export-to-sqlite.py | |
parent | 6efb943b8616ec53a5e444193dccf1af9ad627b5 (diff) | |
parent | f13570e7e830ca4fbf4869015af8492b8918445e (diff) |
Merge tag 'for-5.14-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-nvidia
Pull Tegra clk driver updates from Thierry Reding:
This contains a few fixes across the board and adds stubs to allow
certain drivers to be compile-tested. One other notable change added
here is that clock enabling no longer deasserts the reset. Drivers are
now supposed to do that explicitly because doing it implicitly can get
in the way of certain power-up sequences.
* tag 'for-5.14-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing()
clk: tegra: Add stubs needed for compile-testing
clk: tegra: Don't deassert reset on enabling clocks
clk: tegra: Mark external clocks as not having reset control
clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
clk: tegra: Don't allow zero clock rate for PLLs
clk: tegra: Halve SCLK rate on Tegra20
clk: tegra: Ensure that PLLU configuration is applied properly
clk: tegra: Fix refcounting of gate clocks
clk: tegra30: Use 300MHz for video decoder by default
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions