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author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-06-09 16:32:25 +0100 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-06-10 15:23:37 +0200 |
commit | 403921373799a133e41b59cb730e2c4239663f51 (patch) | |
tree | fec4b0c9d1df4248401a44eccc86db5ab79bd8e0 /tools/perf/scripts/python/export-to-sqlite.py | |
parent | 6efb943b8616ec53a5e444193dccf1af9ad627b5 (diff) |
dt-bindings: clock: Add r9a07g044 CPG Clock Definitions
Define RZ/G2L (R9A07G044) Clock Pulse Generator Core Clock
and module clock outputs, as listed in Table 8.3 ("Clock List")
of the RZ/G2L Hardware User's Manual (Rev.0.42, Feb.2021).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210609153230.6967-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions