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| author | Michał Mirosław <mirq-linux@rere.qmqm.pl> | 2017-09-19 04:48:10 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-11-01 15:00:06 +0100 |
| commit | 54eff2264d3e9fd7e3987de1d7eba1d3581c631e (patch) | |
| tree | efc64cd2a02c839a6fb1a657da81ab76ec7cfdf2 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | d80a32fe98b7ce428669b774c3d10ecae3bc6e6d (diff) | |
clk: tegra: Fix cclk_lp divisor register
According to comments in code and common sense, cclk_lp uses its
own divisor, not cclk_g's.
Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30")
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions