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| author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2018-10-12 16:48:34 +0900 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-12-04 10:29:51 +0100 |
| commit | 7cf3a216a2b3a672cad3e498c186c9333bdff90a (patch) | |
| tree | 21d8500e3bd49df0b499dc5a5805cde560703cbb /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 396bc9d40d694befa1c2c88f9873afc62a189b5f (diff) | |
clk: renesas: r8a77990: Correct parent clock of DU
According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock
of the DU module clocks on R-Car E3 is S1D1.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 3570a2af473789c5 ("clk: renesas: cpg-mssr: Add support for R-Car E3")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions