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| author | Boris Brezillon <boris.brezillon@bootlin.com> | 2019-07-30 11:56:53 +0300 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-08-28 12:40:30 +0300 |
| commit | ad3bba06b63697fd47525a13d29e8ac0312b0302 (patch) | |
| tree | ce76e7f61efac373a9d726800685885209d4ea01 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 641edddb4f43e8adfd851aea3e48ba35c3b81f4a (diff) | |
mtd: spi-nor: Add the SPI_NOR_XSR_RDY flag
S3AN flashes use a specific opcode to read the status register.
We currently use the SPI_S3AN flag to decide whether this specific
SR read opcode should be used, but SPI_S3AN is about to disappear, so
let's add a new flag.
Note that we use the same bit as SPI_S3AN implies SPI_NOR_XSR_RDY and
vice versa.
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions