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| author | Vignesh Raghavendra <vigneshr@ti.com> | 2019-06-25 13:27:45 +0530 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2019-06-27 19:48:08 +0200 |
| commit | d7865933af9ed38f39cf085e1def44b637109999 (patch) | |
| tree | 674a0195f1a3eb40e47010ad78240bc29be77050 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | dcc7d3446a0fa19bd7e8074920b8f9ef3b7ec00c (diff) | |
dt-bindings: mtd: Add bindings for TI's AM654 HyperBus memory controller
Add binding documentation for TI's HyperBus memory controller present on
AM654 SoC.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions