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| author | Sia Jee Heng <jee.heng.sia@intel.com> | 2021-01-25 09:32:53 +0800 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2021-02-01 15:08:16 +0530 |
| commit | f74b3025506046e8662ebb2026697d7755b1d6ff (patch) | |
| tree | 0a44cb7d468d9c3f85b3ac01e649974e7287e9f0 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 425c8a53e87478de2012c94208d7e6c59213d5ca (diff) | |
dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers
Add support for Intel KeemBay AxiDMA BYTE and HALFWORD registers
programming.
Intel KeemBay AxiDMA supports data transfer between device to memory
and memory to device operations.
This code is needed by I2C, I3C, I2S, SPI and UART which uses FIFO
size of 8bits and 16bits to perform memory to device data transfer
operation. 0-padding functionality is provided to avoid
pre-processing of data on CPU.
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Link: https://lore.kernel.org/r/20210125013255.25799-16-jee.heng.sia@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions