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author | Taimur Hassan <syed.hassan@amd.com> | 2021-01-15 17:34:34 -0500 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2021-02-02 12:12:09 -0500 |
commit | fd952d436446cffdf97a61bf456a0987011e42e0 (patch) | |
tree | 8fd3a8b7c148f0246316aea94de4e82d379951be /tools/perf/scripts/python/export-to-sqlite.py | |
parent | c64b0d6bb5d0d40e399e11a3cab02f0f7759bf9f (diff) |
drm/amd/display: Workaround for some legacy DP-VGA dongles
[Why]
Maximum resolution is 1440*900 when connecting to FHD monitor via some DP-VGA
dongles. The display EDID reading fails over AUX/I2C via DP->VGA dongle, and
this leads to the maximum resolution 1920*1080 cannot be obtained from EDID.
[How]
Provide a workaround for some legacy DP-VGA dongles with a longer aux delay.
Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions