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authorTony Luck <tony.luck@intel.com>2020-10-30 12:04:00 -0700
committerBorislav Petkov <bp@suse.de>2020-11-02 11:15:59 +0100
commit68299a42f84288537ee3420c431ac0115ccb90b1 (patch)
treea799950b549bf767c61be95bcc8f83275b86bd7e /tools/perf/scripts/python/exported-sql-viewer.py
parent633cdaf29ec4aae29868320adb3a4f1c5b8c0eac (diff)
x86/mce: Enable additional error logging on certain Intel CPUs
The Xeon versions of Sandy Bridge, Ivy Bridge and Haswell support an optional additional error logging mode which is enabled by an MSR. Previously, this mode was enabled from the mcelog(8) tool via /dev/cpu, but userspace should not be poking at MSRs. So move the enabling into the kernel. [ bp: Correct the explanation why this is done. ] Suggested-by: Boris Petkov <bp@alien8.de> Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20201030190807.GA13884@agluck-desk2.amr.corp.intel.com
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