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| author | José Roberto de Souza <jose.souza@intel.com> | 2019-01-17 12:55:47 -0800 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2019-01-22 16:33:12 -0800 |
| commit | cc8853f57e00511f46386c8e7910e00c5b2e58ea (patch) | |
| tree | 8e79fe65691f1fc987f34846287eebf8a151b736 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 47c6cd54efde71b0e904cd41593978c109660430 (diff) | |
drm/i915: Add PSR2 selective update status registers and bits definitions
This register contains how many blocks was sent in the past selective
updates.
Those registers are not kept set all the times but polling it after flip
can show the values corresponding to the last 8 frames.
v2: Improved macros(Dhinakaran)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190117205548.28378-3-jose.souza@intel.com
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions