diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2016-09-15 14:57:38 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-09-16 16:03:42 -0700 |
| commit | d832fdd9b2d685b8166f37c03d53b9872d77ed54 (patch) | |
| tree | 63fdd4f0d41cfb189abdcb333c735d8705161413 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | cb80ec768a0db73743a6f8b5d94c0b52b97e3ca4 (diff) | |
clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks
The LCD controller and HDMI controller use the LCDx-CHy and HDMI clocks
to generate their dot clocks. To be able to generate a full range of
possible clock rates, the parent PLL clock rates should also be changed.
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions