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| author | Joshua Aberback <joshua.aberback@amd.com> | 2021-01-21 02:33:31 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-02-02 12:12:15 -0500 |
| commit | e2dcd9b8b803b927b4cbc59d91c4088334a248bb (patch) | |
| tree | fae84e4c79f52d8dcd46247a4a943729ecda2b5f /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | fd952d436446cffdf97a61bf456a0987011e42e0 (diff) | |
drm/amd/display: Better handling of dummy p-state table
[Why]
Some scenarios where we use a UCLK frequency in between dummy p-state table
entries result in a p-state hang, due to the table not having a close
enough match, so the default DPM0 latency is used, which can be too long to
support dummy p-state switching in these scenarios.
[How]
- old: match if current freq is within +- margin of table entry
- new: find largest table entry that is lower than current freq + margin
- lower than DPM0 will still use DPM0
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions