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| author | Ondrej Jirman <megous@megous.com> | 2019-06-04 17:40:36 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-06-05 13:49:05 +0200 |
| commit | f167675486c37b88620d344fbb12d06e34f11d47 (patch) | |
| tree | b9ddbcba7e5fe4c03d3520be48105f4381dc9abd /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | fcdf445ff42f036d22178b49cf64e92d527c1330 (diff) | |
clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
The current code defines W1 clock gate to be at 0x1cc, overlaying it
with the IR gate.
Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
causing interrupt floods on H6 (because interrupt flags can't be cleared,
due to IR module's bus being disabled).
Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions