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authorDouglas Anderson <dianders@chromium.org>2022-02-04 14:06:07 -0800
committerBjorn Andersson <bjorn.andersson@linaro.org>2022-02-04 16:29:45 -0600
commit116f7cc43d28ccd621ff1fecc9526c65dde28dcd (patch)
treee9087a265d74ec97d3e43f71c2466ee0c221b044 /tools/perf/scripts/python/mem-phys-addr.py
parent067b2b3616cd5ed924b51064bcaab23ea1ffd18b (diff)
arm64: dts: qcom: sc7280: Add herobrine-r1
Add the new herobrine-r1. Note that this is pretty much a re-design compared to herobrine-r0 so we don't attempt any dtsi to share stuff between them. This patch attempts to define things at 3 levels: 1. The Qcard level. Herobrine includes a Qcard PCB and the Qcard PCB is supposed to be the same (modulo stuffing options) across multiple boards, so trying to define what's there hopefully makes sense. NOTE that newer "CRD" boards from Qualcomm also use Qcard. When support for CRD3 is added hopefully it can use the Qcard include (and perhaps we should even evaluate it using herobrine.dtsi?) 2. The herobrine "baseboard" level. Right now most stuff is here with the exception of things that we _know_ will be different per board. We know that not all boards will have the same set of eMMC, nvme, and SD. We also know that the exact pin names are likely to be different. 3. The actual "board" level, AKA herobrine-rev1. NOTES: - This boots to command prompt. We're still waiting on the PWM driver. - This assumes LTE for now. Once it's clear how WiFi-only SKUs will work we expect some small changes. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220204140550.v4.1.I5604b7af908e8bbe709ac037a6a8a6ba8a2bfa94@changeid
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