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| author | Eugen Hristev <eugen.hristev@microchip.com> | 2019-11-12 07:19:56 +0000 |
|---|---|---|
| committer | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2019-12-09 20:23:43 +0100 |
| commit | 5d4c3cfb63fe311dfa592dc20995907429f6710b (patch) | |
| tree | d85e4c4c0d8f4dd2275f9d8ad0c0523434d9f9f1 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | c963e34f5ac6fab4913e3806e97bfdf089cb4cc6 (diff) | |
ARM: dts: at91: sama5d27_wlsom1: add SAMA5D27 wlsom1 and wlsom1-ek
This is the addition of a new Evaluation Kit the SAMA5D27-WLSOM1-EK.
It's based on the Microchip WireLess SoM which contains the
SAMA5D27 LPDDR2 2Gbits SiP.
[nicolas.ferre@microchip.com]: initial implementation
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[eugen.hristev@microchip.com]: ported to new kernel version,
[eugen.hristev@microchip.com]: addition of peripherals (adc, pmic, qspi, uart)
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lore.kernel.org/r/1573543139-8533-4-git-send-email-eugen.hristev@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions