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authorChristoph Hellwig <hch@lst.de>2019-07-03 09:54:44 -0700
committerChristoph Hellwig <hch@lst.de>2019-07-09 13:44:44 -0700
commit7637de311bd2124b298a072852448b940d8a34b9 (patch)
treeaf68ae72def48f858e4f961b382c8bd6b3021c48 /tools/perf/scripts/python/mem-phys-addr.py
parentbfac8e9f55cf62a000b643a0081488badbe92d96 (diff)
nvme-pci: limit max_hw_sectors based on the DMA max mapping size
When running a NVMe device that is attached to a addressing challenged PCIe root port that requires bounce buffering, our request sizes can easily overflow the swiotlb bounce buffer size. Limit the maximum I/O size to the limit exposed by the DMA mapping subsystem. Signed-off-by: Christoph Hellwig <hch@lst.de> Reported-by: Atish Patra <Atish.Patra@wdc.com> Tested-by: Atish Patra <Atish.Patra@wdc.com> Reviewed-by: Sagi Grimberg <sagi@grimberg.me>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
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