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| author | Clément Péron <peron.clem@gmail.com> | 2018-05-03 17:32:07 +0200 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2018-05-07 11:21:18 -0700 |
| commit | 675c7215aacf54242b2e8bc64bab698abbe764db (patch) | |
| tree | 044ee9c301ba9152df0f895a04dd264e3e243c7a /tools/perf/scripts/python/stackcollapse.py | |
| parent | 60cc43fc888428bb2f18f08997432d426a243338 (diff) | |
ARM: dts: cygnus: fix irq type for arm global timer
As per ARM documentation
PPI(0) ID27 - global timer interrupt is rising-edge sensitive.
set IRQ triggering type to IRQ_TYPE_EDGE_RISING for ARM Global timers.
Fixes: c9ad7bc5fe3 ("ARM: dts: Enable Broadcom Cygnus SoC")
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions