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| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-11-10 20:15:51 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-19 11:27:58 +0100 |
| commit | 1abd04480866cead7b4129bd03246315b4575334 (patch) | |
| tree | 077d4a5076fd6fb3a6742ebcd5b55d18b587a2e3 /tools/perf/scripts/python/syscall-counts.py | |
| parent | a31cf51bf6b4bf78ccb1c9fb40ea6231cf3df433 (diff) | |
clk: renesas: rcar-gen3: Add SDnH clock
Currently a pass-through clock but we will make it a real divider clock
in the next patches.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions