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| author | Chao Peng <chao.p.peng@linux.intel.com> | 2018-10-24 16:05:12 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2018-12-21 11:28:35 +0100 |
| commit | 2ef444f1600bfc2d8522df0f537aafef79befa7e (patch) | |
| tree | 1bdc097495a69ed493a21ef07cb07e77db0da902 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 86f5201df0d3e3efc78d3eac7fc5a59b813287cd (diff) | |
KVM: x86: Add Intel PT context switch for each vcpu
Load/Store Intel Processor Trace register in context switch.
MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS.
In Host-Guest mode, we need load/resore PT MSRs only when PT
is enabled in guest.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions