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authorThierry Reding <treding@nvidia.com>2015-03-23 10:36:45 +0100
committerThierry Reding <treding@nvidia.com>2015-11-24 16:52:21 +0100
commit742af7e7a0a132afe85cc7b8ac82fd20c7b63743 (patch)
treec6179304b19e6478b714c026aba5fdfd9c559c20 /tools/perf/scripts/python/syscall-counts.py
parent0f279ebdf3ce5cd3ee23010a46680dca93282e34 (diff)
arm64: tegra: Add Tegra210 support
Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
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