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| author | Dmitry Osipenko <digetx@gmail.com> | 2019-12-18 21:59:57 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-01-10 15:41:54 +0100 |
| commit | 834f1d6cf3647e804e7a80569e42ee7fbee50eb1 (patch) | |
| tree | 82ce14bb53a11c1acee25c378b7c7b42fd932f50 /tools/perf/scripts/python/syscall-counts.py | |
| parent | ceffd1040ac0e3e661a6604bb018897c438fb340 (diff) | |
ARM: dts: tegra20: paz00: Add memory timings
PAZ00 board has two variants of DDR2 SDRAM devices for External Memory:
one is Hynix HY5PS1G831CLFP-Y5 and the other is Micron MT47H128M8CF-25:H.
The Micron variant doesn't have official timings in the wild, hence only
timings for the Hynix are added. The memory frequency-scaling was tested
using the Tegra20 devfreq driver.
Tested-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions