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| author | Guo Ren <guoren@linux.alibaba.com> | 2020-12-20 03:39:27 +0000 |
|---|---|---|
| committer | Guo Ren <guoren@linux.alibaba.com> | 2021-01-12 09:52:40 +0800 |
| commit | 8d11f21a73e662fa11f39447de629cd8caa485c9 (patch) | |
| tree | 5aa937f17bd6579d02cb046c34f812b1e41e5a18 /tools/perf/scripts/python/syscall-counts.py | |
| parent | f92ddfb7b5415536e4fe4c7a4868737954159374 (diff) | |
csky: Fixup barrier design
Remove shareable bit for ordering barrier, just keep ordering
in current hart is enough for SMP. Using three continuous
sync.is as PTW barrier to prevent speculative PTW in 860
microarchitecture.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions