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| author | Damien Lespiau <damien.lespiau@intel.com> | 2015-03-06 18:50:51 +0000 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-03-17 22:30:07 +0100 |
| commit | d14c03431340d0913f067ab18b6444e0f41d4f80 (patch) | |
| tree | 5358e700e45e1d23fb29ad92f8e926267847d556 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 510e6fdd8f796666ec6a8539b01b5e5e72913046 (diff) | |
drm/i915/skl: Restore pipe interrupt registers after power well enabling
The pipe interrupt registers are in the actual pipe power well, so we
need to restore them when re-enable the corresponding power well.
I've also copied what we do on HSW/BDW for VGA, even if the we haven't
enabled unclaimed registers just yet.
v2: Don't run skl_power_well_post_enable() if the power well is already
enabled (Paulo)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions