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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2021-11-10 08:20:18 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-15 10:47:18 +0100 |
| commit | dc446cba4301bbe2dbe16711091635d987626410 (patch) | |
| tree | 5d40577f915b3dafb8d0720e01b0e6300924fa4d /tools/perf/scripts/python/syscall-counts.py | |
| parent | 073da9e7c768b0d81f9ce22cc907227450612d88 (diff) | |
clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros
Rename the macros CLK_PLL2_DIV16->CLK_PLL2_DIV2_8 and
CLK_PLL2_DIV20->CLK_PLL2_DIV2_10 to match the clock tree mentioned in
the hardware manual(Rev.1.00 Sep, 2021).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211110082019.28554-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions