diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/include/nvfw')
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvfw/pmu.h | 31 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvfw/sec2.h | 22 |
2 files changed, 53 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvfw/pmu.h b/drivers/gpu/drm/nouveau/include/nvfw/pmu.h index 6e86ce31f963..f808998e2ea1 100644 --- a/drivers/gpu/drm/nouveau/include/nvfw/pmu.h +++ b/drivers/gpu/drm/nouveau/include/nvfw/pmu.h @@ -1,8 +1,28 @@ #ifndef __NVFW_PMU_H__ #define __NVFW_PMU_H__ +#define NV_PMU_UNIT_INIT 0x07 #define NV_PMU_UNIT_ACR 0x0a +struct nv_pmu_init_msg { + struct nv_falcon_msg hdr; +#define NV_PMU_INIT_MSG_INIT 0x00 + u8 msg_type; + + u8 pad; + u16 os_debug_entry_point; + + struct { + u16 size; + u16 offset; + u8 index; + u8 pad; + } queue_info[5]; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; +}; + struct nv_pmu_acr_cmd { struct nv_falcon_cmd hdr; #define NV_PMU_ACR_CMD_INIT_WPR_REGION 0x00 @@ -16,6 +36,17 @@ struct nv_pmu_acr_msg { u8 msg_type; }; +struct nv_pmu_acr_init_wpr_region_cmd { + struct nv_pmu_acr_cmd cmd; + u32 region_id; + u32 wpr_offset; +}; + +struct nv_pmu_acr_init_wpr_region_msg { + struct nv_pmu_acr_msg msg; + u32 error_code; +}; + struct nv_pmu_acr_bootstrap_falcon_cmd { struct nv_pmu_acr_cmd cmd; #define NV_PMU_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0x00000000 diff --git a/drivers/gpu/drm/nouveau/include/nvfw/sec2.h b/drivers/gpu/drm/nouveau/include/nvfw/sec2.h index 2f7460fe1b76..80753cfa4cb3 100644 --- a/drivers/gpu/drm/nouveau/include/nvfw/sec2.h +++ b/drivers/gpu/drm/nouveau/include/nvfw/sec2.h @@ -1,8 +1,30 @@ #ifndef __NVFW_SEC2_H__ #define __NVFW_SEC2_H__ +#define NV_SEC2_UNIT_INIT 0x01 #define NV_SEC2_UNIT_ACR 0x08 +struct nv_sec2_init_msg { + struct nv_falcon_msg hdr; +#define NV_SEC2_INIT_MSG_INIT 0x00 + u8 msg_type; + + u8 num_queues; + u16 os_debug_entry_point; + + struct { + u32 offset; + u16 size; + u8 index; +#define NV_SEC2_INIT_MSG_QUEUE_ID_CMDQ 0x00 +#define NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ 0x01 + u8 id; + } queue_info[2]; + + u32 sw_managed_area_offset; + u16 sw_managed_area_size; +}; + struct nv_sec2_acr_cmd { struct nv_falcon_cmd hdr; #define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON 0x00 |