| Age | Commit message (Expand) | Author |
|---|
| 2019-06-19 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 | Thomas Gleixner |
| 2018-05-31 | ARM: spectre-v2: harden branch predictor on context switches | Russell King |
| 2015-06-12 | Merge branches 'arnd-fixes', 'clk', 'misc', 'v7' and 'fixes' into for-next | Russell King |
| 2015-06-01 | ARM: redo TTBR setup code for LPAE | Russell King |
| 2015-05-08 | ARM: 8353/1: mm: Fix Cortex-A8 erratum 430973 segfaults for bootloaders and m... | Tony Lindgren |
| 2015-04-14 | ARM: proc-v7: avoid errata 430973 workaround for non-Cortex A8 CPUs | Russell King |
| 2014-07-18 | ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+ | Russell King |
| 2014-02-10 | ARM: 7954/1: mm: remove remaining domain support from ARMv6 | Will Deacon |
| 2013-07-22 | ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2 | Will Deacon |
| 2013-07-14 | arm: delete __cpuinit/__CPUINIT usage from all ARM users | Paul Gortmaker |
| 2013-04-03 | ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead | Will Deacon |
| 2013-02-16 | ARM: 7650/1: mm: replace direct access to mm->context.id with new macro | Ben Dooks |
| 2012-11-09 | ARM: mm: introduce present, faulting entries for PAGE_NONE | Will Deacon |
| 2012-11-09 | ARM: mm: introduce L_PTE_VALID for page table entries | Will Deacon |
| 2012-11-09 | ARM: mm: don't use the access flag permissions mechanism for classic MMU | Will Deacon |
| 2012-07-09 | ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current process | Will Deacon |
| 2012-04-17 | ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUs | Catalin Marinas |
| 2012-04-17 | ARM: Use TTBR1 instead of reserved context ID | Will Deacon |
| 2011-12-08 | ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.S | Catalin Marinas |
