Age | Commit message (Expand) | Author |
2019-09-05 | riscv: move the TLB flush logic out of line | Christoph Hellwig |
2019-09-05 | riscv: cleanup riscv_cpuid_to_hartid_mask | Christoph Hellwig |
2019-08-30 | RISC-V: Implement sparsemem | Logan Gunthorpe |
2019-08-30 | riscv: Using CSR numbers to access CSRs | Bin Meng |
2019-07-18 | Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g... | Linus Torvalds |
2019-07-09 | RISC-V: Setup initial page tables in two stages | Anup Patel |
2019-07-08 | Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git... | Linus Torvalds |
2019-07-04 | riscv: remove free_initrd_mem | Christoph Hellwig |
2019-07-04 | riscv: ccache: Remove unused variable | Yash Shah |
2019-07-03 | riscv: Introduce huge page support for 32/64bit kernel | Alexandre Ghiti |
2019-07-01 | RISC-V: Fix memory reservation in setup_bootmem() | Anup Patel |
2019-06-26 | riscv: mm: Fix code comment | ShihPo Hung |
2019-06-17 | Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/ke... | Linus Torvalds |
2019-06-17 | riscv: mm: synchronize MMU after pte change | ShihPo Hung |
2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner |
2019-05-29 | signal/riscv: Remove tsk parameter from do_trap | Eric W. Biederman |
2019-05-24 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120 | Thomas Gleixner |
2019-05-21 | treewide: Add SPDX license identifier - Makefile/Kconfig | Thomas Gleixner |
2019-05-19 | Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/ker... | Linus Torvalds |
2019-05-16 | riscv: fix locking violation in page fault handler | Andreas Schwab |
2019-05-16 | RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs | Yash Shah |
2019-05-16 | riscv: move switch_mm to its own file | Gary Guo |
2019-05-16 | riscv: move flush_icache_{all,mm} to cacheflush.c | Gary Guo |
2019-05-16 | RISC-V: Access CSRs using CSR numbers | Anup Patel |
2019-05-14 | riscv: switch over to generic free_initmem() | Mike Rapoport |
2019-04-10 | RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems | Anup Patel |
2019-03-26 | RISC-V: Always compile mm/init.c with cmodel=medany and notrace | Anup Patel |
2019-02-21 | RISC-V: Free-up initrd in free_initrd_mem() | Anup Patel |
2019-02-21 | RISC-V: Implement compile-time fixed mappings | Anup Patel |
2019-02-21 | RISC-V: Move setup_vm() to mm/init.c | Anup Patel |
2019-02-21 | RISC-V: Move setup_bootmem() to mm/init.c | Anup Patel |
2019-01-23 | riscv: fixup max_low_pfn with PFN_DOWN. | Guo Ren |
2018-10-31 | mm: remove include/linux/bootmem.h | Mike Rapoport |
2018-10-31 | memblock: rename free_all_bootmem to memblock_free_all | Mike Rapoport |
2018-10-22 | RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremap | Vincent Chen |
2018-08-17 | mm: convert return type of handle_mm_fault() caller to vm_fault_t | Souptick Joarder |
2018-07-04 | RISC-V: Add conditional macro for zone of DMA32 | Zong Li |
2018-02-07 | Merge tag 'riscv-for-linus-4.16-merge_window' of git://git.kernel.org/pub/scm... | Linus Torvalds |
2018-01-31 | Merge branch 'work.whack-a-mole' of git://git.kernel.org/pub/scm/linux/kernel... | Linus Torvalds |
2018-01-30 | riscv: rename sptbr to satp | Christoph Hellwig |
2018-01-30 | riscv: don't read back satp in paging_init | Christoph Hellwig |
2018-01-30 | riscv: add ZONE_DMA32 | Christoph Hellwig |
2018-01-07 | riscv: rename SR_* constants to match the spec | Christoph Hellwig |
2017-12-04 | riscv: use linux/uaccess.h, not asm/uaccess.h... | Al Viro |
2017-12-01 | RISC-V: Fixes for clean allmodconfig build | Palmer Dabbelt |
2017-11-30 | RISC-V: Flush I$ when making a dirty page executable | Andrew Waterman |
2017-11-30 | RISC-V: io.h: type fixes for warnings | Olof Johansson |
2017-09-26 | RISC-V: Build Infrastructure | Palmer Dabbelt |
2017-09-26 | RISC-V: Paging and MMU | Palmer Dabbelt |
2017-09-26 | RISC-V: Device, timer, IRQs, and the SBI | Palmer Dabbelt |