| Age | Commit message (Expand) | Author |
|---|
| 2021-09-09 | Merge tag 'cxl-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl... | Linus Torvalds |
| 2021-09-07 | cxl/registers: Fix Documentation warning | Dan Williams |
| 2021-09-07 | cxl/pmem: Fix Documentation warning | Dan Williams |
| 2021-09-07 | cxl/pci: Fix debug message in cxl_probe_regs() | Li Qiang (Johnny Li) |
| 2021-09-07 | cxl/pci: Fix lockdown level | Dan Williams |
| 2021-09-07 | cxl/acpi: Do not add DSDT disabled ACPI0016 host bridge ports | Alison Schofield |
| 2021-08-10 | cxl/mem: Adjust ram/pmem range to represent DPA ranges | Ira Weiny |
| 2021-08-10 | cxl/mem: Account for partitionable space in ram/pmem ranges | Ira Weiny |
| 2021-08-07 | cxl/pci: Store memory capacity values | Ira Weiny |
| 2021-08-06 | cxl/pci: Simplify register setup | Ben Widawsky |
| 2021-08-06 | cxl/pci: Ignore unknown register block types | Ben Widawsky |
| 2021-08-06 | cxl/core: Move memdev management to core | Ben Widawsky |
| 2021-08-06 | cxl/pci: Introduce cdevm_file_operations | Dan Williams |
| 2021-08-06 | cxl/core: Move register mapping infrastructure | Dan Williams |
| 2021-08-06 | cxl/core: Move pmem functionality | Dan Williams |
| 2021-08-06 | cxl/core: Improve CXL core kernel docs | Ben Widawsky |
| 2021-08-06 | cxl: Move cxl_core to new directory | Ben Widawsky |
| 2021-07-21 | bus: Make remove callback return void | Uwe Kleine-König |
| 2021-06-17 | cxl/pci: Rename CXL REGLOC ID | Ben Widawsky |
| 2021-06-17 | cxl/acpi: Use the ACPI CFMWS to create static decoder objects | Alison Schofield |
| 2021-06-17 | cxl/acpi: Add the Host Bridge base address to CXL port objects | Alison Schofield |
| 2021-06-15 | cxl/pmem: Register 'pmem' / cxl_nvdimm devices | Dan Williams |
| 2021-06-15 | cxl/pmem: Add initial infrastructure for pmem support | Dan Williams |
| 2021-06-15 | cxl/core: Add cxl-bus driver infrastructure | Dan Williams |
| 2021-06-14 | cxl/pci: Add media provisioning required commands | Ben Widawsky |
| 2021-06-12 | cxl/component_regs: Fix offset | Ben Widawsky |
| 2021-06-12 | cxl/hdm: Fix decoder count calculation | Ben Widawsky |
| 2021-06-09 | cxl/acpi: Introduce cxl_decoder objects | Dan Williams |
| 2021-06-09 | cxl/acpi: Enumerate host bridge root ports | Dan Williams |
| 2021-06-09 | cxl/acpi: Add downstream port data to cxl_port instances | Dan Williams |
| 2021-06-09 | cxl/Kconfig: Default drivers to CONFIG_CXL_BUS | Dan Williams |
| 2021-06-09 | cxl/acpi: Introduce the root of a cxl_port topology | Dan Williams |
| 2021-06-05 | cxl/pci: Fixup devm_cxl_iomap_block() to take a 'struct device *' | Dan Williams |
| 2021-06-05 | cxl/pci: Add HDM decoder capabilities | Ben Widawsky |
| 2021-06-05 | cxl/pci: Reserve individual register block regions | Ira Weiny |
| 2021-06-05 | cxl/pci: Map registers based on capabilities | Ira Weiny |
| 2021-06-05 | cxl/pci: Reserve all device regions at once | Ira Weiny |
| 2021-06-05 | cxl/pci: Introduce cxl_decode_register_block() | Ira Weiny |
| 2021-05-26 | cxl/mem: Get rid of @cxlm.base | Ben Widawsky |
| 2021-05-26 | cxl/mem: Move register locator logic into reg setup | Ben Widawsky |
| 2021-05-26 | cxl/mem: Split creation from mapping in probe | Ben Widawsky |
| 2021-05-26 | cxl/mem: Use dev instead of pdev->dev | Ben Widawsky |
| 2021-05-26 | cxl/mem: Demarcate vendor specific capability IDs | Ben Widawsky |
| 2021-05-26 | cxl/pci.c: Add a 'label_storage_size' attribute to the memdev | Vishal Verma |
| 2021-05-26 | cxl: Rename mem to pci | Ben Widawsky |
| 2021-05-14 | cxl/core: Refactor CXL register lookup for bridge reuse | Dan Williams |
| 2021-05-14 | cxl/core: Rename bus.c to core.c | Dan Williams |
| 2021-05-14 | cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices | Dan Williams |
| 2021-05-14 | cxl/mem: Move some definitions to mem.h | Dan Williams |
| 2021-04-16 | cxl/mem: Fix memory device capacity probing | Dan Williams |
