staging: brcm80211: use enum identifiers in srom variable tables

In the srom variable tables fields were identified using string
identifiers. This has been replaced by enumeration identifiers.

Reported-by: Johannes Berg <johannes@sipsolutions.net>
Reviewed-by: Roland Vossen <rvossen@broadcom.com>
Reviewed-by: Alwin Beukers <alwin@broadcom.com>
Signed-off-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 704 insertions, 647 deletions

diff --git a/drivers/staging/brcm80211/brcmsmac/srom.c b/drivers/staging/brcm80211/brcmsmac/srom.c
index c7a6e654704..f014044b699 100644
--- a/drivers/staging/brcm80211/brcmsmac/srom.c
+++ b/drivers/staging/brcm80211/brcmsmac/srom.c
@@ -365,7 +365,7 @@
 #define	MAXSZ_NVRAM_VARS	4096
 
 struct brcms_sromvar {
-	const char *name;
+	enum brcms_srom_id varid;
 	u32 revmask;
 	u32 flags;
 	u16 off;
@@ -392,393 +392,720 @@ struct brcms_varbuf {
  *   Other entries must have non-NULL name.
  */
 static const struct brcms_sromvar pci_sromvars[] = {
-	{"devid", 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID, 0xffff},
-	{"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK},
-	{"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
-	{"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
-	{"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
-	{"boardflags", 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
-	{"", 0, 0, SROM_BFL2, 0xffff},
-	{"boardflags", 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
-	{"", 0, 0, SROM3_BFL2, 0xffff},
-	{"boardflags", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0, 0xffff},
-	{"", 0, 0, SROM4_BFL1, 0xffff},
-	{"boardflags", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0, 0xffff},
-	{"", 0, 0, SROM5_BFL1, 0xffff},
-	{"boardflags", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 0xffff},
-	{"", 0, 0, SROM8_BFL1, 0xffff},
-	{"boardflags2", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2, 0xffff},
-	{"", 0, 0, SROM4_BFL3, 0xffff},
-	{"boardflags2", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2, 0xffff},
-	{"", 0, 0, SROM5_BFL3, 0xffff},
-	{"boardflags2", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 0xffff},
-	{"", 0, 0, SROM8_BFL3, 0xffff},
-	{"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
-	{"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
-	{"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff},
-	{"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff},
-	{"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff},
-	{"boardnum", 0xffffff00, 0, SROM8_MACLO, 0xffff},
-	{"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
-	{"regrev", 0x00000008, 0, SROM_OPO, 0xff00},
-	{"regrev", 0x00000010, 0, SROM4_REGREV, 0x00ff},
-	{"regrev", 0x000000e0, 0, SROM5_REGREV, 0x00ff},
-	{"regrev", 0xffffff00, 0, SROM8_REGREV, 0x00ff},
-	{"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
-	{"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
-	{"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
-	{"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
-	{"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
-	{"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
-	{"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
-	{"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
-	{"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
-	{"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
-	{"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
-	{"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
-	{"ledbh0", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
-	{"ledbh1", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
-	{"ledbh2", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
-	{"ledbh3", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
-	{"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
-	{"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
-	{"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
-	{"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff},
-	{"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
-	{"pa0b0", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
-	{"pa0b1", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
-	{"pa0b2", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
-	{"pa0itssit", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
-	{"pa0maxpwr", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
-	{"opo", 0x0000000c, 0, SROM_OPO, 0x00ff},
-	{"opo", 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
-	{"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
-	{"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff},
-	{"aa2g", 0xffffff00, 0, SROM8_AA, 0x00ff},
-	{"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
-	{"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00},
-	{"aa5g", 0xffffff00, 0, SROM8_AA, 0xff00},
-	{"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff},
-	{"ag1", 0x0000000e, 0, SROM_AG10, 0xff00},
-	{"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff},
-	{"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00},
-	{"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff},
-	{"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00},
-	{"ag0", 0xffffff00, 0, SROM8_AG10, 0x00ff},
-	{"ag1", 0xffffff00, 0, SROM8_AG10, 0xff00},
-	{"ag2", 0xffffff00, 0, SROM8_AG32, 0x00ff},
-	{"ag3", 0xffffff00, 0, SROM8_AG32, 0xff00},
-	{"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
-	{"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
-	{"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
-	{"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
-	{"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
-	{"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
-	{"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
-	{"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
-	{"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
-	{"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00},
-	{"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
-	{"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
-	{"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
-	{"pa1b0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
-	{"pa1b1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
-	{"pa1b2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
-	{"pa1lob0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
-	{"pa1lob1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
-	{"pa1lob2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
-	{"pa1hib0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
-	{"pa1hib1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
-	{"pa1hib2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
-	{"pa1itssit", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
-	{"pa1maxpwr", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
-	{"pa1lomaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
-	{"pa1himaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
-	{"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
-	{"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
-	{"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
-	{"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
-	{"bxa2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
-	{"rssisav2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
-	{"rssismc2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
-	{"rssismf2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
-	{"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
-	{"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
-	{"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
-	{"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
-	{"bxa5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
-	{"rssisav5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
-	{"rssismc5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
-	{"rssismf5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
-	{"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff},
-	{"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00},
-	{"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
-	{"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00},
-	{"tri2g", 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
-	{"tri5g", 0xffffff00, 0, SROM8_TRI52G, 0xff00},
-	{"tri5gl", 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
-	{"tri5gh", 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
-	{"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
-	{"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
-	{"rxpo2g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
-	{"rxpo5g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
-	{"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK},
-	{"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK},
-	{"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK},
-	{"txchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK},
-	{"rxchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK},
-	{"antswitch", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK},
-	{"tssipos2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK},
-	{"extpagain2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK},
-	{"pdetrange2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK},
-	{"triso2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
-	{"antswctl2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK},
-	{"tssipos5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK},
-	{"extpagain5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK},
-	{"pdetrange5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK},
-	{"triso5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
-	{"antswctl5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK},
-	{"tempthresh", 0xffffff00, 0, SROM8_THERMAL, 0xff00},
-	{"tempoffset", 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
-	{"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff},
-	{"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
-	{"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
-	{"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
-	{"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
-	{"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
-	{"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
-	{"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
-	{"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
-	{"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
-	{"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
-	{"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
-	{"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
-	{"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
-	{"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
-	{"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
-
-	{"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
-	{"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
-	{"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
-	{"ccode", 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
-	{"macaddr", 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
-	{"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
-	{"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
-	{"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
-	{"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff},
-	{"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff},
-	{"leddc", 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 0xffff},
-	{"leddc", 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC, 0xffff},
-	{"leddc", 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC, 0xffff},
-	{"leddc", 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC, 0xffff},
-	{"rawtempsense", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff},
-	{"measpower", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00},
-	{"tempsense_slope", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
+	{BRCMS_SROM_DEVID, 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID,
+	 0xffff},
+	{BRCMS_SROM_BOARDREV, 0x0000000e, SRFL_PRHEX, SROM_AABREV,
+	 SROM_BR_MASK},
+	{BRCMS_SROM_BOARDREV, 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
+	{BRCMS_SROM_BOARDREV, 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
+	{BRCMS_SROM_BOARDFLAGS, 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
+	{BRCMS_SROM_BOARDFLAGS, 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL,
+	 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM_BFL2, 0xffff},
+	{BRCMS_SROM_BOARDFLAGS, 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL,
+	 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM3_BFL2, 0xffff},
+	{BRCMS_SROM_BOARDFLAGS, 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0,
+	 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM4_BFL1, 0xffff},
+	{BRCMS_SROM_BOARDFLAGS, 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0,
+	 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM5_BFL1, 0xffff},
+	{BRCMS_SROM_BOARDFLAGS, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0,
+	 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM8_BFL1, 0xffff},
+	{BRCMS_SROM_BOARDFLAGS2, 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2,
+	 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM4_BFL3, 0xffff},
+	{BRCMS_SROM_BOARDFLAGS2, 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2,
+	 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM5_BFL3, 0xffff},
+	{BRCMS_SROM_BOARDFLAGS2, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2,
+	 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM8_BFL3, 0xffff},
+	{BRCMS_SROM_BOARDTYPE, 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
+	{BRCMS_SROM_BOARDNUM, 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
+	{BRCMS_SROM_BOARDNUM, 0x00000008, 0, SROM3_MACLO, 0xffff},
+	{BRCMS_SROM_BOARDNUM, 0x00000010, 0, SROM4_MACLO, 0xffff},
+	{BRCMS_SROM_BOARDNUM, 0x000000e0, 0, SROM5_MACLO, 0xffff},
+	{BRCMS_SROM_BOARDNUM, 0xffffff00, 0, SROM8_MACLO, 0xffff},
+	{BRCMS_SROM_CC, 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
+	{BRCMS_SROM_REGREV, 0x00000008, 0, SROM_OPO, 0xff00},
+	{BRCMS_SROM_REGREV, 0x00000010, 0, SROM4_REGREV, 0x00ff},
+	{BRCMS_SROM_REGREV, 0x000000e0, 0, SROM5_REGREV, 0x00ff},
+	{BRCMS_SROM_REGREV, 0xffffff00, 0, SROM8_REGREV, 0x00ff},
+	{BRCMS_SROM_LEDBH0, 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
+	{BRCMS_SROM_LEDBH1, 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
+	{BRCMS_SROM_LEDBH2, 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
+	{BRCMS_SROM_LEDBH3, 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
+	{BRCMS_SROM_LEDBH0, 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
+	{BRCMS_SROM_LEDBH1, 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
+	{BRCMS_SROM_LEDBH2, 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
+	{BRCMS_SROM_LEDBH3, 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
+	{BRCMS_SROM_LEDBH0, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
+	{BRCMS_SROM_LEDBH1, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
+	{BRCMS_SROM_LEDBH2, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
+	{BRCMS_SROM_LEDBH3, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
+	{BRCMS_SROM_LEDBH0, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
+	{BRCMS_SROM_LEDBH1, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
+	{BRCMS_SROM_LEDBH2, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
+	{BRCMS_SROM_LEDBH3, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
+	{BRCMS_SROM_PA0B0, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
+	{BRCMS_SROM_PA0B1, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
+	{BRCMS_SROM_PA0B2, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
+	{BRCMS_SROM_PA0ITSSIT, 0x0000000e, 0, SROM_ITT, 0x00ff},
+	{BRCMS_SROM_PA0MAXPWR, 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
+	{BRCMS_SROM_PA0B0, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
+	{BRCMS_SROM_PA0B1, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
+	{BRCMS_SROM_PA0B2, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
+	{BRCMS_SROM_PA0ITSSIT, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
+	{BRCMS_SROM_PA0MAXPWR, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
+	{BRCMS_SROM_OPO, 0x0000000c, 0, SROM_OPO, 0x00ff},
+	{BRCMS_SROM_OPO, 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
+	{BRCMS_SROM_AA2G, 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
+	{BRCMS_SROM_AA2G, 0x000000f0, 0, SROM4_AA, 0x00ff},
+	{BRCMS_SROM_AA2G, 0xffffff00, 0, SROM8_AA, 0x00ff},
+	{BRCMS_SROM_AA5G, 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
+	{BRCMS_SROM_AA5G, 0x000000f0, 0, SROM4_AA, 0xff00},
+	{BRCMS_SROM_AA5G, 0xffffff00, 0, SROM8_AA, 0xff00},
+	{BRCMS_SROM_AG0, 0x0000000e, 0, SROM_AG10, 0x00ff},
+	{BRCMS_SROM_AG1, 0x0000000e, 0, SROM_AG10, 0xff00},
+	{BRCMS_SROM_AG0, 0x000000f0, 0, SROM4_AG10, 0x00ff},
+	{BRCMS_SROM_AG1, 0x000000f0, 0, SROM4_AG10, 0xff00},
+	{BRCMS_SROM_AG2, 0x000000f0, 0, SROM4_AG32, 0x00ff},
+	{BRCMS_SROM_AG3, 0x000000f0, 0, SROM4_AG32, 0xff00},
+	{BRCMS_SROM_AG0, 0xffffff00, 0, SROM8_AG10, 0x00ff},
+	{BRCMS_SROM_AG1, 0xffffff00, 0, SROM8_AG10, 0xff00},
+	{BRCMS_SROM_AG2, 0xffffff00, 0, SROM8_AG32, 0x00ff},
+	{BRCMS_SROM_AG3, 0xffffff00, 0, SROM8_AG32, 0xff00},
+	{BRCMS_SROM_PA1B0, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
+	{BRCMS_SROM_PA1B1, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
+	{BRCMS_SROM_PA1B2, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
+	{BRCMS_SROM_PA1LOB0, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
+	{BRCMS_SROM_PA1LOB1, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
+	{BRCMS_SROM_PA1LOB2, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
+	{BRCMS_SROM_PA1HIB0, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
+	{BRCMS_SROM_PA1HIB1, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
+	{BRCMS_SROM_PA1HIB2, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
+	{BRCMS_SROM_PA1ITSSIT, 0x0000000e, 0, SROM_ITT, 0xff00},
+	{BRCMS_SROM_PA1MAXPWR, 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
+	{BRCMS_SROM_PA1LOMAXPWR, 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
+	{BRCMS_SROM_PA1HIMAXPWR, 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
+	{BRCMS_SROM_PA1B0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
+	{BRCMS_SROM_PA1B1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
+	{BRCMS_SROM_PA1B2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
+	{BRCMS_SROM_PA1LOB0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
+	{BRCMS_SROM_PA1LOB1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
+	{BRCMS_SROM_PA1LOB2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
+	{BRCMS_SROM_PA1HIB0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
+	{BRCMS_SROM_PA1HIB1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
+	{BRCMS_SROM_PA1HIB2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
+	{BRCMS_SROM_PA1ITSSIT, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
+	{BRCMS_SROM_PA1MAXPWR, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
+	{BRCMS_SROM_PA1LOMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
+	{BRCMS_SROM_PA1HIMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
+	{BRCMS_SROM_BXA2G, 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
+	{BRCMS_SROM_RSSISAV2G, 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
+	{BRCMS_SROM_RSSISMC2G, 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
+	{BRCMS_SROM_RSSISMF2G, 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
+	{BRCMS_SROM_BXA2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
+	{BRCMS_SROM_RSSISAV2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
+	{BRCMS_SROM_RSSISMC2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
+	{BRCMS_SROM_RSSISMF2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
+	{BRCMS_SROM_BXA5G, 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
+	{BRCMS_SROM_RSSISAV5G, 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
+	{BRCMS_SROM_RSSISMC5G, 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
+	{BRCMS_SROM_RSSISMF5G, 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
+	{BRCMS_SROM_BXA5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
+	{BRCMS_SROM_RSSISAV5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
+	{BRCMS_SROM_RSSISMC5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
+	{BRCMS_SROM_RSSISMF5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
+	{BRCMS_SROM_TRI2G, 0x00000008, 0, SROM_TRI52G, 0x00ff},
+	{BRCMS_SROM_TRI5G, 0x00000008, 0, SROM_TRI52G, 0xff00},
+	{BRCMS_SROM_TRI5GL, 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
+	{BRCMS_SROM_TRI5GH, 0x00000008, 0, SROM_TRI5GHL, 0xff00},
+	{BRCMS_SROM_TRI2G, 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
+	{BRCMS_SROM_TRI5G, 0xffffff00, 0, SROM8_TRI52G, 0xff00},
+	{BRCMS_SROM_TRI5GL, 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
+	{BRCMS_SROM_TRI5GH, 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
+	{BRCMS_SROM_RXPO2G, 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
+	{BRCMS_SROM_RXPO5G, 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
+	{BRCMS_SROM_RXPO2G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
+	{BRCMS_SROM_RXPO5G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
+	{BRCMS_SROM_TXCHAIN, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
+	 SROM4_TXCHAIN_MASK},
+	{BRCMS_SROM_RXCHAIN, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
+	 SROM4_RXCHAIN_MASK},
+	{BRCMS_SROM_ANTSWITCH, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
+	 SROM4_SWITCH_MASK},
+	{BRCMS_SROM_TXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
+	 SROM4_TXCHAIN_MASK},
+	{BRCMS_SROM_RXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
+	 SROM4_RXCHAIN_MASK},
+	{BRCMS_SROM_ANTSWITCH, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
+	 SROM4_SWITCH_MASK},
+	{BRCMS_SROM_TSSIPOS2G, 0xffffff00, 0, SROM8_FEM2G,
+	 SROM8_FEM_TSSIPOS_MASK},
+	{BRCMS_SROM_EXTPAGAIN2G, 0xffffff00, 0, SROM8_FEM2G,
+	 SROM8_FEM_EXTPA_GAIN_MASK},
+	{BRCMS_SROM_PDETRANGE2G, 0xffffff00, 0, SROM8_FEM2G,
+	 SROM8_FEM_PDET_RANGE_MASK},
+	{BRCMS_SROM_TRISO2G, 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
+	{BRCMS_SROM_ANTSWCTL2G, 0xffffff00, 0, SROM8_FEM2G,
+	 SROM8_FEM_ANTSWLUT_MASK},
+	{BRCMS_SROM_TSSIPOS5G, 0xffffff00, 0, SROM8_FEM5G,
+	 SROM8_FEM_TSSIPOS_MASK},
+	{BRCMS_SROM_EXTPAGAIN5G, 0xffffff00, 0, SROM8_FEM5G,
+	 SROM8_FEM_EXTPA_GAIN_MASK},
+	{BRCMS_SROM_PDETRANGE5G, 0xffffff00, 0, SROM8_FEM5G,
+	 SROM8_FEM_PDET_RANGE_MASK},
+	{BRCMS_SROM_TRISO5G, 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
+	{BRCMS_SROM_ANTSWCTL5G, 0xffffff00, 0, SROM8_FEM5G,
+	 SROM8_FEM_ANTSWLUT_MASK},
+	{BRCMS_SROM_TEMPTHRESH, 0xffffff00, 0, SROM8_THERMAL, 0xff00},
+	{BRCMS_SROM_TEMPOFFSET, 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
+	{BRCMS_SROM_TXPID2GA0, 0x000000f0, 0, SROM4_TXPID2G, 0x00ff},
+	{BRCMS_SROM_TXPID2GA1, 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
+	{BRCMS_SROM_TXPID2GA2, 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
+	{BRCMS_SROM_TXPID2GA3, 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
+	{BRCMS_SROM_TXPID5GA0, 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
+	{BRCMS_SROM_TXPID5GA1, 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
+	{BRCMS_SROM_TXPID5GA2, 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
+	{BRCMS_SROM_TXPID5GA3, 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
+	{BRCMS_SROM_TXPID5GLA0, 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
+	{BRCMS_SROM_TXPID5GLA1, 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
+	{BRCMS_SROM_TXPID5GLA2, 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
+	{BRCMS_SROM_TXPID5GLA3, 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
+	{BRCMS_SROM_TXPID5GHA0, 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
+	{BRCMS_SROM_TXPID5GHA1, 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
+	{BRCMS_SROM_TXPID5GHA2, 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
+	{BRCMS_SROM_TXPID5GHA3, 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
+
+	{BRCMS_SROM_CCODE, 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
+	{BRCMS_SROM_CCODE, 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
+	{BRCMS_SROM_CCODE, 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
+	{BRCMS_SROM_CCODE, 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
+	{BRCMS_SROM_MACADDR, 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
+	{BRCMS_SROM_MACADDR, 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
+	{BRCMS_SROM_MACADDR, 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
+	{BRCMS_SROM_MACADDR, 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
+	{BRCMS_SROM_IL0MACADDR, 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0,
+	 0xffff},
+	{BRCMS_SROM_ET1MACADDR, 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1,
+	 0xffff},
+	{BRCMS_SROM_LEDDC, 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC,
+	 0xffff},
+	{BRCMS_SROM_LEDDC, 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC,
+	 0xffff},
+	{BRCMS_SROM_LEDDC, 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC,
+	 0xffff},
+	{BRCMS_SROM_LEDDC, 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC,
+	 0xffff},
+	{BRCMS_SROM_RAWTEMPSENSE, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
+	 0x01ff},
+	{BRCMS_SROM_MEASPOWER, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
+	 0xfe00},
+	{BRCMS_SROM_TEMPSENSE_SLOPE, 0xffffff00, SRFL_PRHEX,
+	 SROM8_TS_SLP_OPT_CORRX, 0x00ff},
+	{BRCMS_SROM_TEMPCORRX, 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
+	 0xfc00},
+	{BRCMS_SROM_TEMPSENSE_OPTION, 0xffffff00, SRFL_PRHEX,
+	 SROM8_TS_SLP_OPT_CORRX, 0x0300},
+	{BRCMS_SROM_FREQOFFSET_CORR, 0xffffff00, SRFL_PRHEX,
+	 SROM8_FOC_HWIQ_IQSWP, 0x000f},
+	{BRCMS_SROM_IQCAL_SWP_DIS, 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
+	 0x0010},
+	{BRCMS_SROM_HW_IQCAL_EN, 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
+	 0x0020},
+	{BRCMS_SROM_PHYCAL_TEMPDELTA, 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA,
 	 0x00ff},
-	{"tempcorrx", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00},
-	{"tempsense_option", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
-	 0x0300},
-	{"freqoffset_corr", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
-	 0x000f},
-	{"iqcal_swp_dis", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010},
-	{"hw_iqcal_en", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020},
-	{"phycal_tempdelta", 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff},
-
-	{"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
-	{"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
-	{"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
-	{"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
-	{"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
-	{"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
-	{"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
-	{"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
-	{"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
-	{"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
-	{"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
-	{"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
-	{"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
-	{"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
-	{"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
-	{"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
-	{"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
-	{"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
-	{"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
-	{"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
-	{"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
-	{"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
-	{"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
-	{"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
-	{"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
-	{"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
-	{"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
-	{"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
-	{"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
-	{"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
-	{"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
-	{"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
-	{"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
-	{"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
-	{"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
-	{"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
-	{"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
-	{"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
-	{"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
-	{"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
-	{"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
-	{"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
-	{"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
-	{"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
-	{"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
-	{"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
-	{"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
-	{"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
-	{"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
-	{"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
-	{"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
-	{"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
-	{"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
-	{"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
-	{"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
-	{"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
-	{"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
-	{"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
-	{"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
-	{"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
-	{"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
-	{"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
-	{"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
-	{"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
-	{"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
-	{"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
-	{"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
-	{"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
-	{"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
-	{"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
-	{"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
-	{"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
-	{"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
-	{"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
-	{"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
-	{"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
-	{"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
-	{"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
-	{"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
-	{"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
-	{"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
-	{"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
-	{"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff},
-	{"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff},
-	{"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff},
-	{"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
-	{"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff},
-	{"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff},
-	{"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff},
-	{"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
+
+	{BRCMS_SROM_CCK2GPO, 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
+	{BRCMS_SROM_CCK2GPO, 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
+	{BRCMS_SROM_OFDM2GPO, 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
+	{BRCMS_SROM_OFDM5GPO, 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
+	{BRCMS_SROM_OFDM5GLPO, 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
+	{BRCMS_SROM_OFDM5GHPO, 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
+	{BRCMS_SROM_OFDM2GPO, 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
+	{BRCMS_SROM_OFDM5GPO, 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
+	{BRCMS_SROM_OFDM5GLPO, 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
+	{BRCMS_SROM_OFDM5GHPO, 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
+	{BRCMS_SROM_MCS2GPO0, 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
+	{BRCMS_SROM_MCS2GPO1, 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
+	{BRCMS_SROM_MCS2GPO2, 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
+	{BRCMS_SROM_MCS2GPO3, 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
+	{BRCMS_SROM_MCS2GPO4, 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
+	{BRCMS_SROM_MCS2GPO5, 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
+	{BRCMS_SROM_MCS2GPO6, 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
+	{BRCMS_SROM_MCS2GPO7, 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
+	{BRCMS_SROM_MCS5GPO0, 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
+	{BRCMS_SROM_MCS5GPO1, 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
+	{BRCMS_SROM_MCS5GPO2, 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
+	{BRCMS_SROM_MCS5GPO3, 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
+	{BRCMS_SROM_MCS5GPO4, 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
+	{BRCMS_SROM_MCS5GPO5, 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
+	{BRCMS_SROM_MCS5GPO6, 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
+	{BRCMS_SROM_MCS5GPO7, 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
+	{BRCMS_SROM_MCS5GLPO0, 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
+	{BRCMS_SROM_MCS5GLPO1, 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
+	{BRCMS_SROM_MCS5GLPO2, 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
+	{BRCMS_SROM_MCS5GLPO3, 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
+	{BRCMS_SROM_MCS5GLPO4, 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
+	{BRCMS_SROM_MCS5GLPO5, 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
+	{BRCMS_SROM_MCS5GLPO6, 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
+	{BRCMS_SROM_MCS5GLPO7, 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
+	{BRCMS_SROM_MCS5GHPO0, 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
+	{BRCMS_SROM_MCS5GHPO1, 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
+	{BRCMS_SROM_MCS5GHPO2, 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
+	{BRCMS_SROM_MCS5GHPO3, 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
+	{BRCMS_SROM_MCS5GHPO4, 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
+	{BRCMS_SROM_MCS5GHPO5, 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
+	{BRCMS_SROM_MCS5GHPO6, 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
+	{BRCMS_SROM_MCS5GHPO7, 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
+	{BRCMS_SROM_MCS2GPO0, 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
+	{BRCMS_SROM_MCS2GPO1, 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
+	{BRCMS_SROM_MCS2GPO2, 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
+	{BRCMS_SROM_MCS2GPO3, 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
+	{BRCMS_SROM_MCS2GPO4, 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
+	{BRCMS_SROM_MCS2GPO5, 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
+	{BRCMS_SROM_MCS2GPO6, 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
+	{BRCMS_SROM_MCS2GPO7, 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
+	{BRCMS_SROM_MCS5GPO0, 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
+	{BRCMS_SROM_MCS5GPO1, 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
+	{BRCMS_SROM_MCS5GPO2, 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
+	{BRCMS_SROM_MCS5GPO3, 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
+	{BRCMS_SROM_MCS5GPO4, 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
+	{BRCMS_SROM_MCS5GPO5, 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
+	{BRCMS_SROM_MCS5GPO6, 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
+	{BRCMS_SROM_MCS5GPO7, 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
+	{BRCMS_SROM_MCS5GLPO0, 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
+	{BRCMS_SROM_MCS5GLPO1, 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
+	{BRCMS_SROM_MCS5GLPO2, 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
+	{BRCMS_SROM_MCS5GLPO3, 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
+	{BRCMS_SROM_MCS5GLPO4, 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
+	{BRCMS_SROM_MCS5GLPO5, 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
+	{BRCMS_SROM_MCS5GLPO6, 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
+	{BRCMS_SROM_MCS5GLPO7, 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
+	{BRCMS_SROM_MCS5GHPO0, 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
+	{BRCMS_SROM_MCS5GHPO1, 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
+	{BRCMS_SROM_MCS5GHPO2, 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
+	{BRCMS_SROM_MCS5GHPO3, 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
+	{BRCMS_SROM_MCS5GHPO4, 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
+	{BRCMS_SROM_MCS5GHPO5, 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
+	{BRCMS_SROM_MCS5GHPO6, 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
+	{BRCMS_SROM_MCS5GHPO7, 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
+	{BRCMS_SROM_CDDPO, 0x000000f0, 0, SROM4_CDDPO, 0xffff},
+	{BRCMS_SROM_STBCPO, 0x000000f0, 0, SROM4_STBCPO, 0xffff},
+	{BRCMS_SROM_BW40PO, 0x000000f0, 0, SROM4_BW40PO, 0xffff},
+	{BRCMS_SROM_BWDUPPO, 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
+	{BRCMS_SROM_CDDPO, 0x00000100, 0, SROM8_CDDPO, 0xffff},
+	{BRCMS_SROM_STBCPO, 0x00000100, 0, SROM8_STBCPO, 0xffff},
+	{BRCMS_SROM_BW40PO, 0x00000100, 0, SROM8_BW40PO, 0xffff},
+	{BRCMS_SROM_BWDUPPO, 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
 
 	/* power per rate from sromrev 9 */
-	{"cckbw202gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
-	{"cckbw20ul2gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
-	{"legofdmbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20,
+	{BRCMS_SROM_CCKBW202GPO, 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
+	{BRCMS_SROM_CCKBW20UL2GPO, 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
+	{BRCMS_SROM_LEGOFDMBW202GPO, 0xfffffe00, SRFL_MORE,
+	 SROM9_2GPO_LOFDMBW20, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
+	{BRCMS_SROM_LEGOFDMBW20UL2GPO, 0xfffffe00, SRFL_MORE,
+	 SROM9_2GPO_LOFDMBW20UL, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
+	{BRCMS_SROM_LEGOFDMBW205GLPO, 0xfffffe00, SRFL_MORE,
+	 SROM9_5GLPO_LOFDMBW20, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
+	{BRCMS_SROM_LEGOFDMBW20UL5GLPO, 0xfffffe00, SRFL_MORE,
+	 SROM9_5GLPO_LOFDMBW20UL, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
+	{BRCMS_SROM_LEGOFDMBW205GMPO, 0xfffffe00, SRFL_MORE,
+	 SROM9_5GMPO_LOFDMBW20, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
+	{BRCMS_SROM_LEGOFDMBW20UL5GMPO, 0xfffffe00, SRFL_MORE,
+	 SROM9_5GMPO_LOFDMBW20UL, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
+	{BRCMS_SROM_LEGOFDMBW205GHPO, 0xfffffe00, SRFL_MORE,
+	 SROM9_5GHPO_LOFDMBW20, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
+	{BRCMS_SROM_LEGOFDMBW20UL5GHPO, 0xfffffe00, SRFL_MORE,
+	 SROM9_5GHPO_LOFDMBW20UL, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
+	{BRCMS_SROM_MCSBW202GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20,
+	 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
+	{BRCMS_SROM_MCSBW20UL2GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL,
 	 0xffff},
-	{"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
-	{"legofdmbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL,
+	{BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
+	{BRCMS_SROM_MCSBW402GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40,
 	 0xffff},
-	{"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
-	{"legofdmbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20,
+	{BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
+	{BRCMS_SROM_MCSBW205GLPO, 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20,
 	 0xffff},
-	{"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
-	{"legofdmbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL,
+	{BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
+	{BRCMS_SROM_MCSBW20UL5GLPO, 0xfffffe00, SRFL_MORE,
+	 SROM9_5GLPO_MCSBW20UL, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
+	{BRCMS_SROM_MCSBW405GLPO, 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40,
 	 0xffff},
-	{"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
-	{"legofdmbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20,
+	{BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
+	{BRCMS_SROM_MCSBW205GMPO, 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20,
 	 0xffff},
-	{"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
-	{"legofdmbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL,
+	{BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
+	{BRCMS_SROM_MCSBW20UL5GMPO, 0xfffffe00, SRFL_MORE,
+	 SROM9_5GMPO_MCSBW20UL, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
+	{BRCMS_SROM_MCSBW405GMPO, 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40,
 	 0xffff},
-	{"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
-	{"legofdmbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20,
+	{BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
+	{BRCMS_SROM_MCSBW205GHPO, 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20,
 	 0xffff},
-	{"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
-	{"legofdmbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL,
+	{BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
+	{BRCMS_SROM_MCSBW20UL5GHPO, 0xfffffe00, SRFL_MORE,
+	 SROM9_5GHPO_MCSBW20UL, 0xffff},
+	{BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
+	{BRCMS_SROM_MCSBW405GHPO, 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40,
 	 0xffff},
-	{"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
-	{"mcsbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff},
-	{"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
-	{"mcsbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff},
-	{"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
-	{"mcsbw402gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff},
-	{"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
-	{"mcsbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff},
-	{"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
-	{"mcsbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20UL,
+	{BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
+	{BRCMS_SROM_MCS32PO, 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
+	{BRCMS_SROM_LEGOFDM40DUPPO, 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
+
+	{BRCMS_SROM_NULL, 0, 0, 0, 0}
+};
+
+static const struct brcms_sromvar perpath_pci_sromvars[] = {
+	{BRCMS_SROM_MAXP2GA0, 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
+	{BRCMS_SROM_ITT2GA0, 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
+	{BRCMS_SROM_ITT5GA0, 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
+	{BRCMS_SROM_PA2GW0A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
+	{BRCMS_SROM_PA2GW1A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
+	{BRCMS_SROM_PA2GW2A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
+	{BRCMS_SROM_PA2GW3A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
+	{BRCMS_SROM_MAXP5GA0, 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
+	{BRCMS_SROM_MAXP5GHA0, 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
+	{BRCMS_SROM_MAXP5GLA0, 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
+	{BRCMS_SROM_PA5GW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
+	{BRCMS_SROM_PA5GW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
+	{BRCMS_SROM_PA5GW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
+	{BRCMS_SROM_PA5GW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
+	{BRCMS_SROM_PA5GLW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
+	{BRCMS_SROM_PA5GLW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1,
+	 0xffff},
+	{BRCMS_SROM_PA5GLW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2,
+	 0xffff},
+	{BRCMS_SROM_PA5GLW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3,
+	 0xffff},
+	{BRCMS_SROM_PA5GHW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
+	{BRCMS_SROM_PA5GHW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1,
+	 0xffff},
+	{BRCMS_SROM_PA5GHW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2,
+	 0xffff},
+	{BRCMS_SROM_PA5GHW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3,
 	 0xffff},
-	{"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
-	{"mcsbw405glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff},
-	{"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
-	{"mcsbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff},
-	{"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
-	{"mcsbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20UL,
+	{BRCMS_SROM_MAXP2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
+	{BRCMS_SROM_ITT2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
+	{BRCMS_SROM_ITT5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
+	{BRCMS_SROM_PA2GW0A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
+	{BRCMS_SROM_PA2GW1A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
+	{BRCMS_SROM_PA2GW2A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
+	{BRCMS_SROM_MAXP5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
+	{BRCMS_SROM_MAXP5GHA0, 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
+	{BRCMS_SROM_MAXP5GLA0, 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
+	{BRCMS_SROM_PA5GW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
+	{BRCMS_SROM_PA5GW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
+	{BRCMS_SROM_PA5GW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
+	{BRCMS_SROM_PA5GLW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
+	{BRCMS_SROM_PA5GLW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1,
 	 0xffff},
-	{"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
-	{"mcsbw405gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff},
-	{"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
-	{"mcsbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff},
-	{"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
-	{"mcsbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20UL,
+	{BRCMS_SROM_PA5GLW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2,
 	 0xffff},
-	{"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
-	{"mcsbw405ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff},
-	{"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
-	{"mcs32po", 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
-	{"legofdm40duppo", 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
+	{BRCMS_SROM_PA5GHW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
+	{BRCMS_SROM_PA5GHW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1,
+	 0xffff},
+	{BRCMS_SROM_PA5GHW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2,
+	 0xffff},
+	{BRCMS_SROM_NULL, 0, 0, 0, 0}
+};
 
-	{NULL, 0, 0, 0, 0}
+struct srom_id_name {
+	enum brcms_srom_id id;
+	const char *name;
 };
 
-static const struct brcms_sromvar perpath_pci_sromvars[] = {
-	{"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
-	{"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
-	{"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
-	{"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
-	{"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
-	{"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
-	{"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
-	{"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
-	{"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
-	{"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
-	{"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
-	{"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
-	{"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
-	{"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
-	{"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
-	{"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff},
-	{"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff},
-	{"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff},
-	{"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
-	{"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff},
-	{"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff},
-	{"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff},
-	{"maxp2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
-	{"itt2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
-	{"itt5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
-	{"pa2gw0a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
-	{"pa2gw1a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
-	{"pa2gw2a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
-	{"maxp5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
-	{"maxp5gha", 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
-	{"maxp5gla", 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
-	{"pa5gw0a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
-	{"pa5gw1a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
-	{"pa5gw2a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
-	{"pa5glw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
-	{"pa5glw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff},
-	{"pa5glw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff},
-	{"pa5ghw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
-	{"pa5ghw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff},
-	{"pa5ghw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff},
-	{NULL, 0, 0, 0, 0}
+static const struct srom_id_name srom_id_map[] = {
+	{ BRCMS_SROM_AA2G, "aa2g" },
+	{ BRCMS_SROM_AA5G, "aa5g" },
+	{ BRCMS_SROM_AG0, "ag0" },
+	{ BRCMS_SROM_AG1, "ag1" },
+	{ BRCMS_SROM_AG2, "ag2" },
+	{ BRCMS_SROM_AG3, "ag3" },
+	{ BRCMS_SROM_ANTSWCTL2G, "antswctl2g" },
+	{ BRCMS_SROM_ANTSWCTL5G, "antswctl5g" },
+	{ BRCMS_SROM_ANTSWITCH, "antswitch" },
+	{ BRCMS_SROM_BOARDFLAGS2, "boardflags2" },
+	{ BRCMS_SROM_BOARDFLAGS, "boardflags" },
+	{ BRCMS_SROM_BOARDNUM, "boardnum" },
+	{ BRCMS_SROM_BOARDREV, "boardrev" },
+	{ BRCMS_SROM_BOARDTYPE, "boardtype" },
+	{ BRCMS_SROM_BW40PO, "bw40po" },
+	{ BRCMS_SROM_BWDUPPO, "bwduppo" },
+	{ BRCMS_SROM_BXA2G, "bxa2g" },
+	{ BRCMS_SROM_BXA5G, "bxa5g" },
+	{ BRCMS_SROM_CC, "cc" },
+	{ BRCMS_SROM_CCK2GPO, "cck2gpo" },
+	{ BRCMS_SROM_CCKBW202GPO, "cckbw202gpo" },
+	{ BRCMS_SROM_CCKBW20UL2GPO, "cckbw20ul2gpo" },
+	{ BRCMS_SROM_CCODE, "ccode" },
+	{ BRCMS_SROM_CDDPO, "cddpo" },
+	{ BRCMS_SROM_DEVID, "devid" },
+	{ BRCMS_SROM_ET1MACADDR, "et1macaddr" },
+	{ BRCMS_SROM_EXTPAGAIN2G, "extpagain2g" },
+	{ BRCMS_SROM_EXTPAGAIN5G, "extpagain5g" },
+	{ BRCMS_SROM_FREQOFFSET_CORR, "freqoffset_corr" },
+	{ BRCMS_SROM_HW_IQCAL_EN, "hw_iqcal_en" },
+	{ BRCMS_SROM_IL0MACADDR, "il0macaddr" },
+	{ BRCMS_SROM_IQCAL_SWP_DIS, "iqcal_swp_dis" },
+	{ BRCMS_SROM_LEDBH0, "ledbh0" },
+	{ BRCMS_SROM_LEDBH1, "ledbh1" },
+	{ BRCMS_SROM_LEDBH2, "ledbh2" },
+	{ BRCMS_SROM_LEDBH3, "ledbh3" },
+	{ BRCMS_SROM_LEDDC, "leddc" },
+	{ BRCMS_SROM_LEGOFDM40DUPPO, "legofdm40duppo" },
+	{ BRCMS_SROM_LEGOFDMBW202GPO, "legofdmbw202gpo" },
+	{ BRCMS_SROM_LEGOFDMBW205GHPO, "legofdmbw205ghpo" },
+	{ BRCMS_SROM_LEGOFDMBW205GLPO, "legofdmbw205glpo" },
+	{ BRCMS_SROM_LEGOFDMBW205GMPO, "legofdmbw205gmpo" },
+	{ BRCMS_SROM_LEGOFDMBW20UL2GPO, "legofdmbw20ul2gpo" },
+	{ BRCMS_SROM_LEGOFDMBW20UL5GHPO, "legofdmbw20ul5ghpo" },
+	{ BRCMS_SROM_LEGOFDMBW20UL5GLPO, "legofdmbw20ul5glpo" },
+	{ BRCMS_SROM_LEGOFDMBW20UL5GMPO, "legofdmbw20ul5gmpo" },
+	{ BRCMS_SROM_MACADDR, "macaddr" },
+	{ BRCMS_SROM_MCS2GPO0, "mcs2gpo0" },
+	{ BRCMS_SROM_MCS2GPO1, "mcs2gpo1" },
+	{ BRCMS_SROM_MCS2GPO2, "mcs2gpo2" },
+	{ BRCMS_SROM_MCS2GPO3, "mcs2gpo3" },
+	{ BRCMS_SROM_MCS2GPO4, "mcs2gpo4" },
+	{ BRCMS_SROM_MCS2GPO5, "mcs2gpo5" },
+	{ BRCMS_SROM_MCS2GPO6, "mcs2gpo6" },
+	{ BRCMS_SROM_MCS2GPO7, "mcs2gpo7" },
+	{ BRCMS_SROM_MCS32PO, "mcs32po" },
+	{ BRCMS_SROM_MCS5GHPO0, "mcs5ghpo0" },
+	{ BRCMS_SROM_MCS5GHPO1, "mcs5ghpo1" },
+	{ BRCMS_SROM_MCS5GHPO2, "mcs5ghpo2" },
+	{ BRCMS_SROM_MCS5GHPO3, "mcs5ghpo3" },
+	{ BRCMS_SROM_MCS5GHPO4, "mcs5ghpo4" },
+	{ BRCMS_SROM_MCS5GHPO5, "mcs5ghpo5" },
+	{ BRCMS_SROM_MCS5GHPO6, "mcs5ghpo6" },
+	{ BRCMS_SROM_MCS5GHPO7, "mcs5ghpo7" },
+	{ BRCMS_SROM_MCS5GLPO0, "mcs5glpo0" },
+	{ BRCMS_SROM_MCS5GLPO1, "mcs5glpo1" },
+	{ BRCMS_SROM_MCS5GLPO2, "mcs5glpo2" },
+	{ BRCMS_SROM_MCS5GLPO3, "mcs5glpo3" },
+	{ BRCMS_SROM_MCS5GLPO4, "mcs5glpo4" },
+	{ BRCMS_SROM_MCS5GLPO5, "mcs5glpo5" },
+	{ BRCMS_SROM_MCS5GLPO6, "mcs5glpo6" },
+	{ BRCMS_SROM_MCS5GLPO7, "mcs5glpo7" },
+	{ BRCMS_SROM_MCS5GPO0, "mcs5gpo0" },
+	{ BRCMS_SROM_MCS5GPO1, "mcs5gpo1" },
+	{ BRCMS_SROM_MCS5GPO2, "mcs5gpo2" },
+	{ BRCMS_SROM_MCS5GPO3, "mcs5gpo3" },
+	{ BRCMS_SROM_MCS5GPO4, "mcs5gpo4" },
+	{ BRCMS_SROM_MCS5GPO5, "mcs5gpo5" },
+	{ BRCMS_SROM_MCS5GPO6, "mcs5gpo6" },
+	{ BRCMS_SROM_MCS5GPO7, "mcs5gpo7" },
+	{ BRCMS_SROM_MCSBW202GPO, "mcsbw202gpo" },
+	{ BRCMS_SROM_MCSBW205GHPO, "mcsbw205ghpo" },
+	{ BRCMS_SROM_MCSBW205GLPO, "mcsbw205glpo" },
+	{ BRCMS_SROM_MCSBW205GMPO, "mcsbw205gmpo" },
+	{ BRCMS_SROM_MCSBW20UL2GPO, "mcsbw20ul2gpo" },
+	{ BRCMS_SROM_MCSBW20UL5GHPO, "mcsbw20ul5ghpo" },
+	{ BRCMS_SROM_MCSBW20UL5GLPO, "mcsbw20ul5glpo" },
+	{ BRCMS_SROM_MCSBW20UL5GMPO, "mcsbw20ul5gmpo" },
+	{ BRCMS_SROM_MCSBW402GPO, "mcsbw402gpo" },
+	{ BRCMS_SROM_MCSBW405GHPO, "mcsbw405ghpo" },
+	{ BRCMS_SROM_MCSBW405GLPO, "mcsbw405glpo" },
+	{ BRCMS_SROM_MCSBW405GMPO, "mcsbw405gmpo" },
+	{ BRCMS_SROM_MEASPOWER, "measpower" },
+	{ BRCMS_SROM_OFDM2GPO, "ofdm2gpo" },
+	{ BRCMS_SROM_OFDM5GHPO, "ofdm5ghpo" },
+	{ BRCMS_SROM_OFDM5GLPO, "ofdm5glpo" },
+	{ BRCMS_SROM_OFDM5GPO, "ofdm5gpo" },
+	{ BRCMS_SROM_OPO, "opo" },
+	{ BRCMS_SROM_PA0B0, "pa0b0" },
+	{ BRCMS_SROM_PA0B1, "pa0b1" },
+	{ BRCMS_SROM_PA0B2, "pa0b2" },
+	{ BRCMS_SROM_PA0ITSSIT, "pa0itssit" },
+	{ BRCMS_SROM_PA0MAXPWR, "pa0maxpwr" },
+	{ BRCMS_SROM_PA1B0, "pa1b0" },
+	{ BRCMS_SROM_PA1B1, "pa1b1" },
+	{ BRCMS_SROM_PA1B2, "pa1b2" },
+	{ BRCMS_SROM_PA1HIB0, "pa1hib0" },
+	{ BRCMS_SROM_PA1HIB1, "pa1hib1" },
+	{ BRCMS_SROM_PA1HIB2, "pa1hib2" },
+	{ BRCMS_SROM_PA1HIMAXPWR, "pa1himaxpwr" },
+	{ BRCMS_SROM_PA1ITSSIT, "pa1itssit" },
+	{ BRCMS_SROM_PA1LOB0, "pa1lob0" },
+	{ BRCMS_SROM_PA1LOB1, "pa1lob1" },
+	{ BRCMS_SROM_PA1LOB2, "pa1lob2" },
+	{ BRCMS_SROM_PA1LOMAXPWR, "pa1lomaxpwr" },
+	{ BRCMS_SROM_PA1MAXPWR, "pa1maxpwr" },
+	{ BRCMS_SROM_PDETRANGE2G, "pdetrange2g" },
+	{ BRCMS_SROM_PDETRANGE5G, "pdetrange5g" },
+	{ BRCMS_SROM_PHYCAL_TEMPDELTA, "phycal_tempdelta" },
+	{ BRCMS_SROM_RAWTEMPSENSE, "rawtempsense" },
+	{ BRCMS_SROM_REV, "sromrev" },
+	{ BRCMS_SROM_REGREV, "regrev" },
+	{ BRCMS_SROM_RSSISAV2G, "rssisav2g" },
+	{ BRCMS_SROM_RSSISAV5G, "rssisav5g" },
+	{ BRCMS_SROM_RSSISMC2G, "rssismc2g" },
+	{ BRCMS_SROM_RSSISMC5G, "rssismc5g" },
+	{ BRCMS_SROM_RSSISMF2G, "rssismf2g" },
+	{ BRCMS_SROM_RSSISMF5G, "rssismf5g" },
+	{ BRCMS_SROM_RXCHAIN, "rxchain" },
+	{ BRCMS_SROM_RXPO2G, "rxpo2g" },
+	{ BRCMS_SROM_RXPO5G, "rxpo5g" },
+	{ BRCMS_SROM_STBCPO, "stbcpo" },
+	{ BRCMS_SROM_TEMPCORRX, "tempcorrx" },
+	{ BRCMS_SROM_TEMPOFFSET, "tempoffset" },
+	{ BRCMS_SROM_TEMPSENSE_OPTION, "tempsense_option" },
+	{ BRCMS_SROM_TEMPSENSE_SLOPE, "tempsense_slope" },
+	{ BRCMS_SROM_TEMPTHRESH, "tempthresh" },
+	{ BRCMS_SROM_TRI2G, "tri2g" },
+	{ BRCMS_SROM_TRI5GH, "tri5gh" },
+	{ BRCMS_SROM_TRI5GL, "tri5gl" },
+	{ BRCMS_SROM_TRI5G, "tri5g" },
+	{ BRCMS_SROM_TRISO2G, "triso2g" },
+	{ BRCMS_SROM_TRISO5G, "triso5g" },
+	{ BRCMS_SROM_TSSIPOS2G, "tssipos2g" },
+	{ BRCMS_SROM_TSSIPOS5G, "tssipos5g" },
+	{ BRCMS_SROM_TXCHAIN, "txchain" },
+	{ BRCMS_SROM_TXPID2GA0, "txpid2ga0" },
+	{ BRCMS_SROM_TXPID2GA1, "txpid2ga1" },
+	{ BRCMS_SROM_TXPID2GA2, "txpid2ga2" },
+	{ BRCMS_SROM_TXPID2GA3, "txpid2ga3" },
+	{ BRCMS_SROM_TXPID5GA0, "txpid5ga0" },
+	{ BRCMS_SROM_TXPID5GA1, "txpid5ga1" },
+	{ BRCMS_SROM_TXPID5GA2, "txpid5ga2" },
+	{ BRCMS_SROM_TXPID5GA3, "txpid5ga3" },
+	{ BRCMS_SROM_TXPID5GHA0, "txpid5gha0" },
+	{ BRCMS_SROM_TXPID5GHA1, "txpid5gha1" },
+	{ BRCMS_SROM_TXPID5GHA2, "txpid5gha2" },
+	{ BRCMS_SROM_TXPID5GHA3, "txpid5gha3" },
+	{ BRCMS_SROM_TXPID5GLA0, "txpid5gla0" },
+	{ BRCMS_SROM_TXPID5GLA1, "txpid5gla1" },
+	{ BRCMS_SROM_TXPID5GLA2, "txpid5gla2" },
+	{ BRCMS_SROM_TXPID5GLA3, "txpid5gla3" },
+	{ BRCMS_SROM_ITT2GA0, "itt2ga0" },
+	{ BRCMS_SROM_ITT2GA1, "itt2ga1" },
+	{ BRCMS_SROM_ITT2GA2, "itt2ga2" },
+	{ BRCMS_SROM_ITT2GA3, "itt2ga3" },
+	{ BRCMS_SROM_ITT5GA0, "itt5ga0" },
+	{ BRCMS_SROM_ITT5GA1, "itt5ga1" },
+	{ BRCMS_SROM_ITT5GA2, "itt5ga2" },
+	{ BRCMS_SROM_ITT5GA3, "itt5ga3" },
+	{ BRCMS_SROM_MAXP2GA0, "maxp2ga0" },
+	{ BRCMS_SROM_MAXP2GA1, "maxp2ga1" },
+	{ BRCMS_SROM_MAXP2GA2, "maxp2ga2" },
+	{ BRCMS_SROM_MAXP2GA3, "maxp2ga3" },
+	{ BRCMS_SROM_MAXP5GA0, "maxp5ga0" },
+	{ BRCMS_SROM_MAXP5GA1, "maxp5ga1" },
+	{ BRCMS_SROM_MAXP5GA2, "maxp5ga2" },
+	{ BRCMS_SROM_MAXP5GA3, "maxp5ga3" },
+	{ BRCMS_SROM_MAXP5GHA0, "maxp5gha0" },
+	{ BRCMS_SROM_MAXP5GHA1, "maxp5gha1" },
+	{ BRCMS_SROM_MAXP5GHA2, "maxp5gha2" },
+	{ BRCMS_SROM_MAXP5GHA3, "maxp5gha3" },
+	{ BRCMS_SROM_MAXP5GLA0, "maxp5gla0" },
+	{ BRCMS_SROM_MAXP5GLA1, "maxp5gla1" },
+	{ BRCMS_SROM_MAXP5GLA2, "maxp5gla2" },
+	{ BRCMS_SROM_MAXP5GLA3, "maxp5gla3" },
+	{ BRCMS_SROM_PA2GW0A0, "pa2gw0a0" },
+	{ BRCMS_SROM_PA2GW0A1, "pa2gw0a1" },
+	{ BRCMS_SROM_PA2GW0A2, "pa2gw0a2" },
+	{ BRCMS_SROM_PA2GW0A3, "pa2gw0a3" },
+	{ BRCMS_SROM_PA2GW1A0, "pa2gw1a0" },
+	{ BRCMS_SROM_PA2GW1A1, "pa2gw1a1" },
+	{ BRCMS_SROM_PA2GW1A2, "pa2gw1a2" },
+	{ BRCMS_SROM_PA2GW1A3, "pa2gw1a3" },
+	{ BRCMS_SROM_PA2GW2A0, "pa2gw2a0" },
+	{ BRCMS_SROM_PA2GW2A1, "pa2gw2a1" },
+	{ BRCMS_SROM_PA2GW2A2, "pa2gw2a2" },
+	{ BRCMS_SROM_PA2GW2A3, "pa2gw2a3" },
+	{ BRCMS_SROM_PA2GW3A0, "pa2gw3a0" },
+	{ BRCMS_SROM_PA2GW3A1, "pa2gw3a1" },
+	{ BRCMS_SROM_PA2GW3A2, "pa2gw3a2" },
+	{ BRCMS_SROM_PA2GW3A3, "pa2gw3a3" },
+	{ BRCMS_SROM_PA5GHW0A0, "pa5ghw0a0" },
+	{ BRCMS_SROM_PA5GHW0A1, "pa5ghw0a1" },
+	{ BRCMS_SROM_PA5GHW0A2, "pa5ghw0a2" },
+	{ BRCMS_SROM_PA5GHW0A3, "pa5ghw0a3" },
+	{ BRCMS_SROM_PA5GHW1A0, "pa5ghw1a0" },
+	{ BRCMS_SROM_PA5GHW1A1, "pa5ghw1a1" },
+	{ BRCMS_SROM_PA5GHW1A2, "pa5ghw1a2" },
+	{ BRCMS_SROM_PA5GHW1A3, "pa5ghw1a3" },
+	{ BRCMS_SROM_PA5GHW2A0, "pa5ghw2a0" },
+	{ BRCMS_SROM_PA5GHW2A1, "pa5ghw2a1" },
+	{ BRCMS_SROM_PA5GHW2A2, "pa5ghw2a2" },
+	{ BRCMS_SROM_PA5GHW2A3, "pa5ghw2a3" },
+	{ BRCMS_SROM_PA5GHW3A0, "pa5ghw3a0" },
+	{ BRCMS_SROM_PA5GHW3A1, "pa5ghw3a1" },
+	{ BRCMS_SROM_PA5GHW3A2, "pa5ghw3a2" },
+	{ BRCMS_SROM_PA5GHW3A3, "pa5ghw3a3" },
+	{ BRCMS_SROM_PA5GLW0A0, "pa5glw0a0" },
+	{ BRCMS_SROM_PA5GLW0A1, "pa5glw0a1" },
+	{ BRCMS_SROM_PA5GLW0A2, "pa5glw0a2" },
+	{ BRCMS_SROM_PA5GLW0A3, "pa5glw0a3" },
+	{ BRCMS_SROM_PA5GLW1A0, "pa5glw1a0" },
+	{ BRCMS_SROM_PA5GLW1A1, "pa5glw1a1" },
+	{ BRCMS_SROM_PA5GLW1A2, "pa5glw1a2" },
+	{ BRCMS_SROM_PA5GLW1A3, "pa5glw1a3" },
+	{ BRCMS_SROM_PA5GLW2A0, "pa5glw2a0" },
+	{ BRCMS_SROM_PA5GLW2A1, "pa5glw2a1" },
+	{ BRCMS_SROM_PA5GLW2A2, "pa5glw2a2" },
+	{ BRCMS_SROM_PA5GLW2A3, "pa5glw2a3" },
+	{ BRCMS_SROM_PA5GLW3A0, "pa5glw3a0" },
+	{ BRCMS_SROM_PA5GLW3A1, "pa5glw3a1" },
+	{ BRCMS_SROM_PA5GLW3A2, "pa5glw3a2" },
+	{ BRCMS_SROM_PA5GLW3A3, "pa5glw3a3" },
+	{ BRCMS_SROM_PA5GW0A0, "pa5gw0a0" },
+	{ BRCMS_SROM_PA5GW0A1, "pa5gw0a1" },
+	{ BRCMS_SROM_PA5GW0A2, "pa5gw0a2" },
+	{ BRCMS_SROM_PA5GW0A3, "pa5gw0a3" },
+	{ BRCMS_SROM_PA5GW1A0, "pa5gw1a0" },
+	{ BRCMS_SROM_PA5GW1A1, "pa5gw1a1" },
+	{ BRCMS_SROM_PA5GW1A2, "pa5gw1a2" },
+	{ BRCMS_SROM_PA5GW1A3, "pa5gw1a3" },
+	{ BRCMS_SROM_PA5GW2A0, "pa5gw2a0" },
+	{ BRCMS_SROM_PA5GW2A1, "pa5gw2a1" },
+	{ BRCMS_SROM_PA5GW2A2, "pa5gw2a2" },
+	{ BRCMS_SROM_PA5GW2A3, "pa5gw2a3" },
+	{ BRCMS_SROM_PA5GW3A0, "pa5gw3a0" },
+	{ BRCMS_SROM_PA5GW3A1, "pa5gw3a1" },
+	{ BRCMS_SROM_PA5GW3A2, "pa5gw3a2" },
+	{ BRCMS_SROM_PA5GW3A3, "pa5gw3a3" },
 };
 
+static const char *get_varname(enum brcms_srom_id id)
+{
+	const struct srom_id_name *entry;
+	int i;
+
+	entry = &srom_id_map[0];
+	for (i = 0; i < ARRAY_SIZE(srom_id_map); i++) {
+		if (entry->id == id)
+			return entry->name;
+		entry++;
+	}
+	return NULL;
+}
+
 /* crc table has the same contents for every device instance, so it can be
  * shared between devices. */
 static u8 brcms_srom_crc8_table[CRC8_TABLE_SIZE];
@@ -908,7 +1235,7 @@ _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, struct brcms_varbuf *b)
 
 	varbuf_append(b, "sromrev=%d", sromrev);
 
-	for (srv = pci_sromvars; srv->name != NULL; srv++) {
+	for (srv = pci_sromvars; srv->varid != BRCMS_SROM_NULL; srv++) {
 		const char *name;
 
 		if ((srv->revmask & sr) == 0)
@@ -918,7 +1245,7 @@ _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, struct brcms_varbuf *b)
 			continue;
 
 		flags = srv->flags;
-		name = srv->name;
+		name = get_varname(srv->varid);
 
 		/* This entry is for mfgc only. Don't generate param for it, */
 		if (flags & SRFL_NOVAR)
@@ -997,8 +1324,8 @@ _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, struct brcms_varbuf *b)
 		}
 
 		for (p = 0; p < MAX_PATH_SROM; p++) {
-			for (srv = perpath_pci_sromvars; srv->name != NULL;
-			     srv++) {
+			for (srv = perpath_pci_sromvars;
+			     srv->varid != BRCMS_SROM_NULL; srv++) {
 				if ((srv->revmask & sr) == 0)
 					continue;
 
@@ -1019,10 +1346,12 @@ _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, struct brcms_varbuf *b)
 					continue;
 
 				if (srv->flags & SRFL_PRHEX)
-					varbuf_append(b, "%s%d=0x%x", srv->name,
+					varbuf_append(b, "%s%d=0x%x",
+						      get_varname(srv->varid),
 						      p, val);
 				else
-					varbuf_append(b, "%s%d=%d", srv->name,
+					varbuf_append(b, "%s%d=%d",
+						      get_varname(srv->varid),
 						      p, val);
 			}
 			pb += psz;
@@ -1244,278 +1573,6 @@ int srom_var_init(struct si_pub *sih, void __iomem *curmap, char **vars,
 	return -EINVAL;
 }
 
-struct srom_id_name {
-	enum brcms_srom_id id;
-	const char *name;
-};
-
-static const struct srom_id_name srom_id_map[] = {
-	{ BRCMS_SROM_AA2G, "aa2g" },
-	{ BRCMS_SROM_AA5G, "aa5g" },
-	{ BRCMS_SROM_AG0, "ag0" },
-	{ BRCMS_SROM_AG1, "ag1" },
-	{ BRCMS_SROM_AG2, "ag2" },
-	{ BRCMS_SROM_AG3, "ag3" },
-	{ BRCMS_SROM_ANTSWCTL2G, "antswctl2g" },
-	{ BRCMS_SROM_ANTSWCTL5G, "antswctl5g" },
-	{ BRCMS_SROM_ANTSWITCH, "antswitch" },
-	{ BRCMS_SROM_BOARDFLAGS2, "boardflags2" },
-	{ BRCMS_SROM_BOARDFLAGS, "boardflags" },
-	{ BRCMS_SROM_BOARDNUM, "boardnum" },
-	{ BRCMS_SROM_BOARDREV, "boardrev" },
-	{ BRCMS_SROM_BOARDTYPE, "boardtype" },
-	{ BRCMS_SROM_BW40PO, "bw40po" },
-	{ BRCMS_SROM_BWDUPPO, "bwduppo" },
-	{ BRCMS_SROM_BXA2G, "bxa2g" },
-	{ BRCMS_SROM_BXA5G, "bxa5g" },
-	{ BRCMS_SROM_CC, "cc" },
-	{ BRCMS_SROM_CCK2GPO, "cck2gpo" },
-	{ BRCMS_SROM_CCKBW202GPO, "cckbw202gpo" },
-	{ BRCMS_SROM_CCKBW20UL2GPO, "cckbw20ul2gpo" },
-	{ BRCMS_SROM_CCODE, "ccode" },
-	{ BRCMS_SROM_CDDPO, "cddpo" },
-	{ BRCMS_SROM_DEVID, "devid" },
-	{ BRCMS_SROM_ET1MACADDR, "et1macaddr" },
-	{ BRCMS_SROM_EXTPAGAIN2G, "extpagain2g" },
-	{ BRCMS_SROM_EXTPAGAIN5G, "extpagain5g" },
-	{ BRCMS_SROM_FREQOFFSET_CORR, "freqoffset_corr" },
-	{ BRCMS_SROM_HW_IQCAL_EN, "hw_iqcal_en" },
-	{ BRCMS_SROM_IL0MACADDR, "il0macaddr" },
-	{ BRCMS_SROM_IQCAL_SWP_DIS, "iqcal_swp_dis" },
-	{ BRCMS_SROM_LEDBH0, "ledbh0" },
-	{ BRCMS_SROM_LEDBH1, "ledbh1" },
-	{ BRCMS_SROM_LEDBH2, "ledbh2" },
-	{ BRCMS_SROM_LEDBH3, "ledbh3" },
-	{ BRCMS_SROM_LEDDC, "leddc" },
-	{ BRCMS_SROM_LEGOFDM40DUPPO, "legofdm40duppo" },
-	{ BRCMS_SROM_LEGOFDMBW202GPO, "legofdmbw202gpo" },
-	{ BRCMS_SROM_LEGOFDMBW205GHPO, "legofdmbw205ghpo" },
-	{ BRCMS_SROM_LEGOFDMBW205GLPO, "legofdmbw205glpo" },
-	{ BRCMS_SROM_LEGOFDMBW205GMPO, "legofdmbw205gmpo" },
-	{ BRCMS_SROM_LEGOFDMBW20UL2GPO, "legofdmbw20ul2gpo" },
-	{ BRCMS_SROM_LEGOFDMBW20UL5GHPO, "legofdmbw20ul5ghpo" },
-	{ BRCMS_SROM_LEGOFDMBW20UL5GLPO, "legofdmbw20ul5glpo" },
-	{ BRCMS_SROM_LEGOFDMBW20UL5GMPO, "legofdmbw20ul5gmpo" },
-	{ BRCMS_SROM_MACADDR, "macaddr" },
-	{ BRCMS_SROM_MCS2GPO0, "mcs2gpo0" },
-	{ BRCMS_SROM_MCS2GPO1, "mcs2gpo1" },
-	{ BRCMS_SROM_MCS2GPO2, "mcs2gpo2" },
-	{ BRCMS_SROM_MCS2GPO3, "mcs2gpo3" },
-	{ BRCMS_SROM_MCS2GPO4, "mcs2gpo4" },
-	{ BRCMS_SROM_MCS2GPO5, "mcs2gpo5" },
-	{ BRCMS_SROM_MCS2GPO6, "mcs2gpo6" },
-	{ BRCMS_SROM_MCS2GPO7, "mcs2gpo7" },
-	{ BRCMS_SROM_MCS32PO, "mcs32po" },
-	{ BRCMS_SROM_MCS5GHPO0, "mcs5ghpo0" },
-	{ BRCMS_SROM_MCS5GHPO1, "mcs5ghpo1" },
-	{ BRCMS_SROM_MCS5GHPO2, "mcs5ghpo2" },
-	{ BRCMS_SROM_MCS5GHPO3, "mcs5ghpo3" },
-	{ BRCMS_SROM_MCS5GHPO4, "mcs5ghpo4" },
-	{ BRCMS_SROM_MCS5GHPO5, "mcs5ghpo5" },
-	{ BRCMS_SROM_MCS5GHPO6, "mcs5ghpo6" },
-	{ BRCMS_SROM_MCS5GHPO7, "mcs5ghpo7" },
-	{ BRCMS_SROM_MCS5GLPO0, "mcs5glpo0" },
-	{ BRCMS_SROM_MCS5GLPO1, "mcs5glpo1" },
-	{ BRCMS_SROM_MCS5GLPO2, "mcs5glpo2" },
-	{ BRCMS_SROM_MCS5GLPO3, "mcs5glpo3" },
-	{ BRCMS_SROM_MCS5GLPO4, "mcs5glpo4" },
-	{ BRCMS_SROM_MCS5GLPO5, "mcs5glpo5" },
-	{ BRCMS_SROM_MCS5GLPO6, "mcs5glpo6" },
-	{ BRCMS_SROM_MCS5GLPO7, "mcs5glpo7" },
-	{ BRCMS_SROM_MCS5GPO0, "mcs5gpo0" },
-	{ BRCMS_SROM_MCS5GPO1, "mcs5gpo1" },
-	{ BRCMS_SROM_MCS5GPO2, "mcs5gpo2" },
-	{ BRCMS_SROM_MCS5GPO3, "mcs5gpo3" },
-	{ BRCMS_SROM_MCS5GPO4, "mcs5gpo4" },
-	{ BRCMS_SROM_MCS5GPO5, "mcs5gpo5" },
-	{ BRCMS_SROM_MCS5GPO6, "mcs5gpo6" },
-	{ BRCMS_SROM_MCS5GPO7, "mcs5gpo7" },
-	{ BRCMS_SROM_MCSBW202GPO, "mcsbw202gpo" },
-	{ BRCMS_SROM_MCSBW205GHPO, "mcsbw205ghpo" },
-	{ BRCMS_SROM_MCSBW205GLPO, "mcsbw205glpo" },
-	{ BRCMS_SROM_MCSBW205GMPO, "mcsbw205gmpo" },
-	{ BRCMS_SROM_MCSBW20UL2GPO, "mcsbw20ul2gpo" },
-	{ BRCMS_SROM_MCSBW20UL5GHPO, "mcsbw20ul5ghpo" },
-	{ BRCMS_SROM_MCSBW20UL5GLPO, "mcsbw20ul5glpo" },
-	{ BRCMS_SROM_MCSBW20UL5GMPO, "mcsbw20ul5gmpo" },
-	{ BRCMS_SROM_MCSBW402GPO, "mcsbw402gpo" },
-	{ BRCMS_SROM_MCSBW405GHPO, "mcsbw405ghpo" },
-	{ BRCMS_SROM_MCSBW405GLPO, "mcsbw405glpo" },
-	{ BRCMS_SROM_MCSBW405GMPO, "mcsbw405gmpo" },
-	{ BRCMS_SROM_MEASPOWER, "measpower" },
-	{ BRCMS_SROM_OFDM2GPO, "ofdm2gpo" },
-	{ BRCMS_SROM_OFDM5GHPO, "ofdm5ghpo" },
-	{ BRCMS_SROM_OFDM5GLPO, "ofdm5glpo" },
-	{ BRCMS_SROM_OFDM5GPO, "ofdm5gpo" },
-	{ BRCMS_SROM_OPO, "opo" },
-	{ BRCMS_SROM_PA0B0, "pa0b0" },
-	{ BRCMS_SROM_PA0B1, "pa0b1" },
-	{ BRCMS_SROM_PA0B2, "pa0b2" },
-	{ BRCMS_SROM_PA0ITSSIT, "pa0itssit" },
-	{ BRCMS_SROM_PA0MAXPWR, "pa0maxpwr" },
-	{ BRCMS_SROM_PA1B0, "pa1b0" },
-	{ BRCMS_SROM_PA1B1, "pa1b1" },
-	{ BRCMS_SROM_PA1B2, "pa1b2" },
-	{ BRCMS_SROM_PA1HIB0, "pa1hib0" },
-	{ BRCMS_SROM_PA1HIB1, "pa1hib1" },
-	{ BRCMS_SROM_PA1HIB2, "pa1hib2" },
-	{ BRCMS_SROM_PA1HIMAXPWR, "pa1himaxpwr" },
-	{ BRCMS_SROM_PA1ITSSIT, "pa1itssit" },
-	{ BRCMS_SROM_PA1LOB0, "pa1lob0" },
-	{ BRCMS_SROM_PA1LOB1, "pa1lob1" },
-	{ BRCMS_SROM_PA1LOB2, "pa1lob2" },
-	{ BRCMS_SROM_PA1LOMAXPWR, "pa1lomaxpwr" },
-	{ BRCMS_SROM_PA1MAXPWR, "pa1maxpwr" },
-	{ BRCMS_SROM_PDETRANGE2G, "pdetrange2g" },
-	{ BRCMS_SROM_PDETRANGE5G, "pdetrange5g" },
-	{ BRCMS_SROM_PHYCAL_TEMPDELTA, "phycal_tempdelta" },
-	{ BRCMS_SROM_RAWTEMPSENSE, "rawtempsense" },
-	{ BRCMS_SROM_REV, "sromrev" },
-	{ BRCMS_SROM_REGREV, "regrev" },
-	{ BRCMS_SROM_RSSISAV2G, "rssisav2g" },
-	{ BRCMS_SROM_RSSISAV5G, "rssisav5g" },
-	{ BRCMS_SROM_RSSISMC2G, "rssismc2g" },
-	{ BRCMS_SROM_RSSISMC5G, "rssismc5g" },
-	{ BRCMS_SROM_RSSISMF2G, "rssismf2g" },
-	{ BRCMS_SROM_RSSISMF5G, "rssismf5g" },
-	{ BRCMS_SROM_RXCHAIN, "rxchain" },
-	{ BRCMS_SROM_RXPO2G, "rxpo2g" },
-	{ BRCMS_SROM_RXPO5G, "rxpo5g" },
-	{ BRCMS_SROM_STBCPO, "stbcpo" },
-	{ BRCMS_SROM_TEMPCORRX, "tempcorrx" },
-	{ BRCMS_SROM_TEMPOFFSET, "tempoffset" },
-	{ BRCMS_SROM_TEMPSENSE_OPTION, "tempsense_option" },
-	{ BRCMS_SROM_TEMPSENSE_SLOPE, "tempsense_slope" },
-	{ BRCMS_SROM_TEMPTHRESH, "tempthresh" },
-	{ BRCMS_SROM_TRI2G, "tri2g" },
-	{ BRCMS_SROM_TRI5GH, "tri5gh" },
-	{ BRCMS_SROM_TRI5GL, "tri5gl" },
-	{ BRCMS_SROM_TRI5G, "tri5g" },
-	{ BRCMS_SROM_TRISO2G, "triso2g" },
-	{ BRCMS_SROM_TRISO5G, "triso5g" },
-	{ BRCMS_SROM_TSSIPOS2G, "tssipos2g" },
-	{ BRCMS_SROM_TSSIPOS5G, "tssipos5g" },
-	{ BRCMS_SROM_TXCHAIN, "txchain" },
-	{ BRCMS_SROM_TXPID2GA0, "txpid2ga0" },
-	{ BRCMS_SROM_TXPID2GA1, "txpid2ga1" },
-	{ BRCMS_SROM_TXPID2GA2, "txpid2ga2" },
-	{ BRCMS_SROM_TXPID2GA3, "txpid2ga3" },
-	{ BRCMS_SROM_TXPID5GA0, "txpid5ga0" },
-	{ BRCMS_SROM_TXPID5GA1, "txpid5ga1" },
-	{ BRCMS_SROM_TXPID5GA2, "txpid5ga2" },
-	{ BRCMS_SROM_TXPID5GA3, "txpid5ga3" },
-	{ BRCMS_SROM_TXPID5GHA0, "txpid5gha0" },
-	{ BRCMS_SROM_TXPID5GHA1, "txpid5gha1" },
-	{ BRCMS_SROM_TXPID5GHA2, "txpid5gha2" },
-	{ BRCMS_SROM_TXPID5GHA3, "txpid5gha3" },
-	{ BRCMS_SROM_TXPID5GLA0, "txpid5gla0" },
-	{ BRCMS_SROM_TXPID5GLA1, "txpid5gla1" },
-	{ BRCMS_SROM_TXPID5GLA2, "txpid5gla2" },
-	{ BRCMS_SROM_TXPID5GLA3, "txpid5gla3" },
-	{ BRCMS_SROM_ITT2GA0, "itt2ga0" },
-	{ BRCMS_SROM_ITT2GA1, "itt2ga1" },
-	{ BRCMS_SROM_ITT2GA2, "itt2ga2" },
-	{ BRCMS_SROM_ITT2GA3, "itt2ga3" },
-	{ BRCMS_SROM_ITT5GA0, "itt5ga0" },
-	{ BRCMS_SROM_ITT5GA1, "itt5ga1" },
-	{ BRCMS_SROM_ITT5GA2, "itt5ga2" },
-	{ BRCMS_SROM_ITT5GA3, "itt5ga3" },
-	{ BRCMS_SROM_MAXP2GA0, "maxp2ga0" },
-	{ BRCMS_SROM_MAXP2GA1, "maxp2ga1" },
-	{ BRCMS_SROM_MAXP2GA2, "maxp2ga2" },
-	{ BRCMS_SROM_MAXP2GA3, "maxp2ga3" },
-	{ BRCMS_SROM_MAXP5GA0, "maxp5ga0" },
-	{ BRCMS_SROM_MAXP5GA1, "maxp5ga1" },
-	{ BRCMS_SROM_MAXP5GA2, "maxp5ga2" },
-	{ BRCMS_SROM_MAXP5GA3, "maxp5ga3" },
-	{ BRCMS_SROM_MAXP5GHA0, "maxp5gha0" },
-	{ BRCMS_SROM_MAXP5GHA1, "maxp5gha1" },
-	{ BRCMS_SROM_MAXP5GHA2, "maxp5gha2" },
-	{ BRCMS_SROM_MAXP5GHA3, "maxp5gha3" },
-	{ BRCMS_SROM_MAXP5GLA0, "maxp5gla0" },
-	{ BRCMS_SROM_MAXP5GLA1, "maxp5gla1" },
-	{ BRCMS_SROM_MAXP5GLA2, "maxp5gla2" },
-	{ BRCMS_SROM_MAXP5GLA3, "maxp5gla3" },
-	{ BRCMS_SROM_PA2GW0A0, "pa2gw0a0" },
-	{ BRCMS_SROM_PA2GW0A1, "pa2gw0a1" },
-	{ BRCMS_SROM_PA2GW0A2, "pa2gw0a2" },
-	{ BRCMS_SROM_PA2GW0A3, "pa2gw0a3" },
-	{ BRCMS_SROM_PA2GW1A0, "pa2gw1a0" },
-	{ BRCMS_SROM_PA2GW1A1, "pa2gw1a1" },
-	{ BRCMS_SROM_PA2GW1A2, "pa2gw1a2" },
-	{ BRCMS_SROM_PA2GW1A3, "pa2gw1a3" },
-	{ BRCMS_SROM_PA2GW2A0, "pa2gw2a0" },
-	{ BRCMS_SROM_PA2GW2A1, "pa2gw2a1" },
-	{ BRCMS_SROM_PA2GW2A2, "pa2gw2a2" },
-	{ BRCMS_SROM_PA2GW2A3, "pa2gw2a3" },
-	{ BRCMS_SROM_PA2GW3A0, "pa2gw3a0" },
-	{ BRCMS_SROM_PA2GW3A1, "pa2gw3a1" },
-	{ BRCMS_SROM_PA2GW3A2, "pa2gw3a2" },
-	{ BRCMS_SROM_PA2GW3A3, "pa2gw3a3" },
-	{ BRCMS_SROM_PA5GHW0A0, "pa5ghw0a0" },
-	{ BRCMS_SROM_PA5GHW0A1, "pa5ghw0a1" },
-	{ BRCMS_SROM_PA5GHW0A2, "pa5ghw0a2" },
-	{ BRCMS_SROM_PA5GHW0A3, "pa5ghw0a3" },
-	{ BRCMS_SROM_PA5GHW1A0, "pa5ghw1a0" },
-	{ BRCMS_SROM_PA5GHW1A1, "pa5ghw1a1" },
-	{ BRCMS_SROM_PA5GHW1A2, "pa5ghw1a2" },
-	{ BRCMS_SROM_PA5GHW1A3, "pa5ghw1a3" },
-	{ BRCMS_SROM_PA5GHW2A0, "pa5ghw2a0" },
-	{ BRCMS_SROM_PA5GHW2A1, "pa5ghw2a1" },
-	{ BRCMS_SROM_PA5GHW2A2, "pa5ghw2a2" },
-	{ BRCMS_SROM_PA5GHW2A3, "pa5ghw2a3" },
-	{ BRCMS_SROM_PA5GHW3A0, "pa5ghw3a0" },
-	{ BRCMS_SROM_PA5GHW3A1, "pa5ghw3a1" },
-	{ BRCMS_SROM_PA5GHW3A2, "pa5ghw3a2" },
-	{ BRCMS_SROM_PA5GHW3A3, "pa5ghw3a3" },
-	{ BRCMS_SROM_PA5GLW0A0, "pa5glw0a0" },
-	{ BRCMS_SROM_PA5GLW0A1, "pa5glw0a1" },
-	{ BRCMS_SROM_PA5GLW0A2, "pa5glw0a2" },
-	{ BRCMS_SROM_PA5GLW0A3, "pa5glw0a3" },
-	{ BRCMS_SROM_PA5GLW1A0, "pa5glw1a0" },
-	{ BRCMS_SROM_PA5GLW1A1, "pa5glw1a1" },
-	{ BRCMS_SROM_PA5GLW1A2, "pa5glw1a2" },
-	{ BRCMS_SROM_PA5GLW1A3, "pa5glw1a3" },
-	{ BRCMS_SROM_PA5GLW2A0, "pa5glw2a0" },
-	{ BRCMS_SROM_PA5GLW2A1, "pa5glw2a1" },
-	{ BRCMS_SROM_PA5GLW2A2, "pa5glw2a2" },
-	{ BRCMS_SROM_PA5GLW2A3, "pa5glw2a3" },
-	{ BRCMS_SROM_PA5GLW3A0, "pa5glw3a0" },
-	{ BRCMS_SROM_PA5GLW3A1, "pa5glw3a1" },
-	{ BRCMS_SROM_PA5GLW3A2, "pa5glw3a2" },
-	{ BRCMS_SROM_PA5GLW3A3, "pa5glw3a3" },
-	{ BRCMS_SROM_PA5GW0A0, "pa5gw0a0" },
-	{ BRCMS_SROM_PA5GW0A1, "pa5gw0a1" },
-	{ BRCMS_SROM_PA5GW0A2, "pa5gw0a2" },
-	{ BRCMS_SROM_PA5GW0A3, "pa5gw0a3" },
-	{ BRCMS_SROM_PA5GW1A0, "pa5gw1a0" },
-	{ BRCMS_SROM_PA5GW1A1, "pa5gw1a1" },
-	{ BRCMS_SROM_PA5GW1A2, "pa5gw1a2" },
-	{ BRCMS_SROM_PA5GW1A3, "pa5gw1a3" },
-	{ BRCMS_SROM_PA5GW2A0, "pa5gw2a0" },
-	{ BRCMS_SROM_PA5GW2A1, "pa5gw2a1" },
-	{ BRCMS_SROM_PA5GW2A2, "pa5gw2a2" },
-	{ BRCMS_SROM_PA5GW2A3, "pa5gw2a3" },
-	{ BRCMS_SROM_PA5GW3A0, "pa5gw3a0" },
-	{ BRCMS_SROM_PA5GW3A1, "pa5gw3a1" },
-	{ BRCMS_SROM_PA5GW3A2, "pa5gw3a2" },
-	{ BRCMS_SROM_PA5GW3A3, "pa5gw3a3" },
-};
-
-static const char *get_varname(enum brcms_srom_id id)
-{
-	const struct srom_id_name *entry;
-	int i;
-
-	entry = &srom_id_map[0];
-	for (i = 0; i < ARRAY_SIZE(srom_id_map); i++) {
-		if (entry->id == id)
-			return entry->name;
-		entry++;
-	}
-	return NULL;
-}
-
 /*
  * Search the name=value vars for a specific one and return its value.
  * Returns NULL if not found.