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authorTomi Valkeinen <tomi.valkeinen@ti.com>2011-09-01 08:20:45 +0100
committerAndy Green <andy.green@linaro.org>2011-09-01 08:20:45 +0100
commita6871e8f1f3c906b37884fb35837546b7c1dc15e (patch)
treeab4677863600acf7476258e66e2c5d46232ac863 /REPORTING-BUGS
parent19a63ba5a43b026d79ccc526a5c5efc20f3006f1 (diff)
OMAP: DSS2: DISPC: Fix minimum PCD valuetilt-3.0-nodspvideo1-11-09-01
The current driver had a hardcoded minimum value of 2 for pixel clock divisor (PCD). This doesn't seem to be right. OMAP4 TRM says that PCD can be 1 when not downscaling, and inverted pixel clock (IPC) is off. OMAP3 TRM says the same, but also in the register descriptions that PCD value 1 is invalid. OMAP2 TRM says PCD 2 is the minimum. OMAP2 is still untested, but for both OMAP3 and OMAP4 PCD of 1 seems to work fine. This patch adds a new DSS feature, FEAT_PARAM_DSS_PCD, which is used to find the minimum and maximum PCD. The minimum is set to 2 for OMAP2, and 1 for OMAP3/4. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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