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authorArnd Bergmann <arnd@arndb.de>2012-02-28 12:42:14 +0000
committerArnd Bergmann <arnd@arndb.de>2012-02-28 12:42:21 +0000
commitfb0b82b32ce17564bc64cede50bf4a3204eecc60 (patch)
tree00b5e466074c6fb373d64c493b3341186024acc7 /arch/arm/common
parenta173fc693b25216c5c834978f4fafd731fd4ff94 (diff)
parent43de6a7dda6e9a7345e218e688f2092f991126f0 (diff)
Merge branch 'board-specific' of git://github.com/hzhuang1/linux into next/boards
* 'board-specific' of git://github.com/hzhuang1/linux: (5 commits) ARM: pxa: add dummy clock for pxa25x and pxa27x ARM: mmp: append irq name of gpio device pxa/hx4700: Fix PXA_GPIO_IRQ_BASE/IRQ_NUM values pxa/hx4700: Add ASIC3 LED support pxa/hx4700: Correct StrataFlash block size discovery (update to v3.3-rc5)
Diffstat (limited to 'arch/arm/common')
-rw-r--r--arch/arm/common/it8152.c7
-rw-r--r--arch/arm/common/pl330.c3
2 files changed, 2 insertions, 8 deletions
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index d1bcd7b13eb..fb1f1cfce60 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -320,13 +320,6 @@ err0:
return -EBUSY;
}
-/*
- * If we set up a device for bus mastering, we need to check the latency
- * timer as we don't have even crappy BIOSes to set it properly.
- * The implementation is from arch/i386/pci/i386.c
- */
-unsigned int pcibios_max_latency = 255;
-
/* ITE bridge requires setting latency timer to avoid early bus access
termination by PCI bus master devices
*/
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c
index d8e44a43047..ff3ad224482 100644
--- a/arch/arm/common/pl330.c
+++ b/arch/arm/common/pl330.c
@@ -1502,12 +1502,13 @@ int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
struct pl330_thread *thrd = ch_id;
struct pl330_dmac *pl330;
unsigned long flags;
- int ret = 0, active = thrd->req_running;
+ int ret = 0, active;
if (!thrd || thrd->free || thrd->dmac->state == DYING)
return -EINVAL;
pl330 = thrd->dmac;
+ active = thrd->req_running;
spin_lock_irqsave(&pl330->lock, flags);