diff options
| author | Changhwan Youn <chaos.youn@samsung.com> | 2011-10-04 17:08:57 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-10-04 18:35:02 +0900 |
| commit | 90a454b4c5ef16ec71797b3dcaf454e604c786a3 (patch) | |
| tree | 11cf8fcec590c912b4cb35a24232337f1f7e1946 /arch/arm/mach-exynos4/cpu.c | |
| parent | b88b1cc72e2bbb55c56f2df55b5ad59a18ad1464 (diff) | |
ARM: EXYNOS4: Add functions for gic interrupt handling
This patch adds two functions for gic interrupt handling.
1. Add interrupt handling of 4 cores.
2. Dynamically set gic bank offset according to the type of soc.
Gic bank offset of EXYNOS4412 is 0x4000 while the offset of
EXYNOS4210 and EXYNOS4212 is 0x8000.
This patch is necessary because EXYNOS4 socs cannot support
GIC register banking as described in commit aab74d3e75364.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos4/cpu.c')
| -rw-r--r-- | arch/arm/mach-exynos4/cpu.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index 940bc12f754..a348434f17b 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -32,6 +32,8 @@ #include <mach/regs-irq.h> #include <mach/regs-pmu.h> +unsigned int gic_bank_offset __read_mostly; + extern int combiner_init(unsigned int combiner_nr, void __iomem *base, unsigned int irq_start); extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); @@ -203,16 +205,18 @@ static void exynos4_gic_irq_fix_base(struct irq_data *d) struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); gic_data->cpu_base = S5P_VA_GIC_CPU + - (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); + (gic_bank_offset * smp_processor_id()); gic_data->dist_base = S5P_VA_GIC_DIST + - (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); + (gic_bank_offset * smp_processor_id()); } void __init exynos4_init_irq(void) { int irq; + gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; + gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base; gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base; |