diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-05-23 15:15:27 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-05-23 15:15:27 -0700 |
commit | 42cd71bf1e3a081b3150018bbf448cb6c8a844a5 (patch) | |
tree | 4a5d2eb0444255e4ad827a76dbd1417dd3876db6 /arch/arm/mach-spear3xx/spear3xx.c | |
parent | f5039935ac685b3b9b8c13fbc33cac8643dee32e (diff) | |
parent | 9a55d9752d8abfc62f1ab05ccc790d22a0c8e7c0 (diff) |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (137 commits)
ARM: bcmring: convert to use sp804 clockevents
ARM: bcmring: convert to sp804 clocksource
ARM: 6912/1: bcmring: Add clkdev table in init_early
clockevents: ARM sp804: obtain sp804 timer rate via clks
clockevents: ARM sp804: allow clockevent name to be specified
clocksource: ARM sp804: obtain sp804 timer rate via clks
clocksource: ARM sp804: allow clocksource name to be specified
clocksource: convert OMAP1 to 32-bit down counting clocksource
clocksource: convert MXS timrotv2 to 32-bit down counting clocksource
clocksource: convert SPEAr platforms 16-bit up counting clocksource
clocksource: convert Integrator/AP 16-bit down counting clocksource
clocksource: convert W90x900 24-bit down counting clocksource
clocksource: convert ARM 32-bit down counting clocksources
clocksource: convert ARM 32-bit up counting clocksources
clocksource: add common mmio clocksource
ARM: update sa1100 to reflect PXA updates
ARM: omap1: convert to using readl/writel instead of volatile struct
ARM: omap1: delete useless interrupt handler
ARM: s5p: consolidate selection of timer register
ARM: 6939/1: fix missing 'cpu_relax()' declaration
...
Diffstat (limited to 'arch/arm/mach-spear3xx/spear3xx.c')
-rw-r--r-- | arch/arm/mach-spear3xx/spear3xx.c | 132 |
1 files changed, 66 insertions, 66 deletions
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index d3ba8ca1bc5..10af45da86a 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c @@ -25,10 +25,10 @@ /* gpio device registration */ static struct pl061_platform_data gpio_plat_data = { .gpio_base = 0, - .irq_base = SPEAR_GPIO_INT_BASE, + .irq_base = SPEAR3XX_GPIO_INT_BASE, }; -struct amba_device gpio_device = { +struct amba_device spear3xx_gpio_device = { .dev = { .init_name = "gpio", .platform_data = &gpio_plat_data, @@ -38,11 +38,11 @@ struct amba_device gpio_device = { .end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, - .irq = {IRQ_BASIC_GPIO, NO_IRQ}, + .irq = {SPEAR3XX_IRQ_BASIC_GPIO, NO_IRQ}, }; /* uart device registration */ -struct amba_device uart_device = { +struct amba_device spear3xx_uart_device = { .dev = { .init_name = "uart", }, @@ -51,7 +51,7 @@ struct amba_device uart_device = { .end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, - .irq = {IRQ_UART, NO_IRQ}, + .irq = {SPEAR3XX_IRQ_UART, NO_IRQ}, }; /* Do spear3xx familiy common initialization part here */ @@ -97,215 +97,215 @@ void __init spear3xx_map_io(void) iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); /* This will initialize clock framework */ - clk_init(); + spear3xx_clk_init(); } /* pad multiplexing support */ /* devices */ -struct pmx_dev_mode pmx_firda_modes[] = { +static struct pmx_dev_mode pmx_firda_modes[] = { { .ids = 0xffffffff, .mask = PMX_FIRDA_MASK, }, }; -struct pmx_dev pmx_firda = { +struct pmx_dev spear3xx_pmx_firda = { .name = "firda", .modes = pmx_firda_modes, .mode_count = ARRAY_SIZE(pmx_firda_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_i2c_modes[] = { +static struct pmx_dev_mode pmx_i2c_modes[] = { { .ids = 0xffffffff, .mask = PMX_I2C_MASK, }, }; -struct pmx_dev pmx_i2c = { +struct pmx_dev spear3xx_pmx_i2c = { .name = "i2c", .modes = pmx_i2c_modes, .mode_count = ARRAY_SIZE(pmx_i2c_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_ssp_cs_modes[] = { +static struct pmx_dev_mode pmx_ssp_cs_modes[] = { { .ids = 0xffffffff, .mask = PMX_SSP_CS_MASK, }, }; -struct pmx_dev pmx_ssp_cs = { +struct pmx_dev spear3xx_pmx_ssp_cs = { .name = "ssp_chip_selects", .modes = pmx_ssp_cs_modes, .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_ssp_modes[] = { +static struct pmx_dev_mode pmx_ssp_modes[] = { { .ids = 0xffffffff, .mask = PMX_SSP_MASK, }, }; -struct pmx_dev pmx_ssp = { +struct pmx_dev spear3xx_pmx_ssp = { .name = "ssp", .modes = pmx_ssp_modes, .mode_count = ARRAY_SIZE(pmx_ssp_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_mii_modes[] = { +static struct pmx_dev_mode pmx_mii_modes[] = { { .ids = 0xffffffff, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_mii = { +struct pmx_dev spear3xx_pmx_mii = { .name = "mii", .modes = pmx_mii_modes, .mode_count = ARRAY_SIZE(pmx_mii_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin0_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin0_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN0_MASK, }, }; -struct pmx_dev pmx_gpio_pin0 = { +struct pmx_dev spear3xx_pmx_gpio_pin0 = { .name = "gpio_pin0", .modes = pmx_gpio_pin0_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin1_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin1_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN1_MASK, }, }; -struct pmx_dev pmx_gpio_pin1 = { +struct pmx_dev spear3xx_pmx_gpio_pin1 = { .name = "gpio_pin1", .modes = pmx_gpio_pin1_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin2_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin2_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN2_MASK, }, }; -struct pmx_dev pmx_gpio_pin2 = { +struct pmx_dev spear3xx_pmx_gpio_pin2 = { .name = "gpio_pin2", .modes = pmx_gpio_pin2_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin3_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin3_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN3_MASK, }, }; -struct pmx_dev pmx_gpio_pin3 = { +struct pmx_dev spear3xx_pmx_gpio_pin3 = { .name = "gpio_pin3", .modes = pmx_gpio_pin3_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin4_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin4_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN4_MASK, }, }; -struct pmx_dev pmx_gpio_pin4 = { +struct pmx_dev spear3xx_pmx_gpio_pin4 = { .name = "gpio_pin4", .modes = pmx_gpio_pin4_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin5_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin5_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN5_MASK, }, }; -struct pmx_dev pmx_gpio_pin5 = { +struct pmx_dev spear3xx_pmx_gpio_pin5 = { .name = "gpio_pin5", .modes = pmx_gpio_pin5_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_uart0_modem_modes[] = { +static struct pmx_dev_mode pmx_uart0_modem_modes[] = { { .ids = 0xffffffff, .mask = PMX_UART0_MODEM_MASK, }, }; -struct pmx_dev pmx_uart0_modem = { +struct pmx_dev spear3xx_pmx_uart0_modem = { .name = "uart0_modem", .modes = pmx_uart0_modem_modes, .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_uart0_modes[] = { +static struct pmx_dev_mode pmx_uart0_modes[] = { { .ids = 0xffffffff, .mask = PMX_UART0_MASK, }, }; -struct pmx_dev pmx_uart0 = { +struct pmx_dev spear3xx_pmx_uart0 = { .name = "uart0", .modes = pmx_uart0_modes, .mode_count = ARRAY_SIZE(pmx_uart0_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_timer_3_4_modes[] = { +static struct pmx_dev_mode pmx_timer_3_4_modes[] = { { .ids = 0xffffffff, .mask = PMX_TIMER_3_4_MASK, }, }; -struct pmx_dev pmx_timer_3_4 = { +struct pmx_dev spear3xx_pmx_timer_3_4 = { .name = "timer_3_4", .modes = pmx_timer_3_4_modes, .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_timer_1_2_modes[] = { +static struct pmx_dev_mode pmx_timer_1_2_modes[] = { { .ids = 0xffffffff, .mask = PMX_TIMER_1_2_MASK, }, }; -struct pmx_dev pmx_timer_1_2 = { +struct pmx_dev spear3xx_pmx_timer_1_2 = { .name = "timer_1_2", .modes = pmx_timer_1_2_modes, .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes), @@ -314,210 +314,210 @@ struct pmx_dev pmx_timer_1_2 = { #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) /* plgpios devices */ -struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { +static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { { .ids = 0x00, .mask = PMX_FIRDA_MASK, }, }; -struct pmx_dev pmx_plgpio_0_1 = { +struct pmx_dev spear3xx_pmx_plgpio_0_1 = { .name = "plgpio 0 and 1", .modes = pmx_plgpio_0_1_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { +static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { { .ids = 0x00, .mask = PMX_UART0_MASK, }, }; -struct pmx_dev pmx_plgpio_2_3 = { +struct pmx_dev spear3xx_pmx_plgpio_2_3 = { .name = "plgpio 2 and 3", .modes = pmx_plgpio_2_3_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { +static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { { .ids = 0x00, .mask = PMX_I2C_MASK, }, }; -struct pmx_dev pmx_plgpio_4_5 = { +struct pmx_dev spear3xx_pmx_plgpio_4_5 = { .name = "plgpio 4 and 5", .modes = pmx_plgpio_4_5_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { +static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { { .ids = 0x00, .mask = PMX_SSP_MASK, }, }; -struct pmx_dev pmx_plgpio_6_9 = { +struct pmx_dev spear3xx_pmx_plgpio_6_9 = { .name = "plgpio 6 to 9", .modes = pmx_plgpio_6_9_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { +static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { { .ids = 0x00, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_plgpio_10_27 = { +struct pmx_dev spear3xx_pmx_plgpio_10_27 = { .name = "plgpio 10 to 27", .modes = pmx_plgpio_10_27_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_28_modes[] = { +static struct pmx_dev_mode pmx_plgpio_28_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN0_MASK, }, }; -struct pmx_dev pmx_plgpio_28 = { +struct pmx_dev spear3xx_pmx_plgpio_28 = { .name = "plgpio 28", .modes = pmx_plgpio_28_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_29_modes[] = { +static struct pmx_dev_mode pmx_plgpio_29_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN1_MASK, }, }; -struct pmx_dev pmx_plgpio_29 = { +struct pmx_dev spear3xx_pmx_plgpio_29 = { .name = "plgpio 29", .modes = pmx_plgpio_29_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_30_modes[] = { +static struct pmx_dev_mode pmx_plgpio_30_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN2_MASK, }, }; -struct pmx_dev pmx_plgpio_30 = { +struct pmx_dev spear3xx_pmx_plgpio_30 = { .name = "plgpio 30", .modes = pmx_plgpio_30_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_31_modes[] = { +static struct pmx_dev_mode pmx_plgpio_31_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN3_MASK, }, }; -struct pmx_dev pmx_plgpio_31 = { +struct pmx_dev spear3xx_pmx_plgpio_31 = { .name = "plgpio 31", .modes = pmx_plgpio_31_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_32_modes[] = { +static struct pmx_dev_mode pmx_plgpio_32_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN4_MASK, }, }; -struct pmx_dev pmx_plgpio_32 = { +struct pmx_dev spear3xx_pmx_plgpio_32 = { .name = "plgpio 32", .modes = pmx_plgpio_32_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_33_modes[] = { +static struct pmx_dev_mode pmx_plgpio_33_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN5_MASK, }, }; -struct pmx_dev pmx_plgpio_33 = { +struct pmx_dev spear3xx_pmx_plgpio_33 = { .name = "plgpio 33", .modes = pmx_plgpio_33_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { +static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { { .ids = 0x00, .mask = PMX_SSP_CS_MASK, }, }; -struct pmx_dev pmx_plgpio_34_36 = { +struct pmx_dev spear3xx_pmx_plgpio_34_36 = { .name = "plgpio 34 to 36", .modes = pmx_plgpio_34_36_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { +static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { { .ids = 0x00, .mask = PMX_UART0_MODEM_MASK, }, }; -struct pmx_dev pmx_plgpio_37_42 = { +struct pmx_dev spear3xx_pmx_plgpio_37_42 = { .name = "plgpio 37 to 42", .modes = pmx_plgpio_37_42_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { +static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { { .ids = 0x00, .mask = PMX_TIMER_1_2_MASK, }, }; -struct pmx_dev pmx_plgpio_43_44_47_48 = { +struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = { .name = "plgpio 43, 44, 47 and 48", .modes = pmx_plgpio_43_44_47_48_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { +static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { { .ids = 0x00, .mask = PMX_TIMER_3_4_MASK, }, }; -struct pmx_dev pmx_plgpio_45_46_49_50 = { +struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = { .name = "plgpio 45, 46, 49 and 50", .modes = pmx_plgpio_45_46_49_50_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes), |