diff options
| author | Colin Cross <ccross@android.com> | 2012-05-07 18:20:34 -0700 |
|---|---|---|
| committer | Colin Cross <ccross@android.com> | 2012-05-07 18:20:34 -0700 |
| commit | f02fac63308349b1dbde468adfd084fdb560eeae (patch) | |
| tree | 35c39e5c3c70e40c52bc18c07a88dd7a1becb649 /arch/arm/mm/cache-l2x0.c | |
| parent | 6ff6845be02be8d53da28d2333a015d54b1234db (diff) | |
| parent | d48b97b403d23f6df0b990cee652bdf9a52337a3 (diff) | |
Merge commit 'v3.4-rc6' into android-3.4
Conflicts:
arch/arm/mm/cache-l2x0.c
arch/arm/mm/mmu.c
Change-Id: If4f371a21c052fa597d107c44b128a093e4a8b91
Diffstat (limited to 'arch/arm/mm/cache-l2x0.c')
| -rw-r--r-- | arch/arm/mm/cache-l2x0.c | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 1edd91cebc9..eaa6847eea4 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -35,6 +35,7 @@ static u32 l2x0_size; static u32 l2x0_cache_id; static unsigned int l2x0_sets; static unsigned int l2x0_ways; +static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; static inline bool is_pl310_rev(int rev) { @@ -71,12 +72,7 @@ static inline void cache_sync(void) { void __iomem *base = l2x0_base; -#ifdef CONFIG_PL310_ERRATA_753970 - /* write to an unmmapped register */ - writel_relaxed(0, base + L2X0_DUMMY_REG); -#else - writel_relaxed(0, base + L2X0_CACHE_SYNC); -#endif + writel_relaxed(0, base + sync_reg_offset); cache_wait(base + L2X0_CACHE_SYNC, 1); } @@ -95,10 +91,13 @@ static inline void l2x0_inv_line(unsigned long addr) } #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) +static inline void debug_writel(unsigned long val) +{ + if (outer_cache.set_debug) + outer_cache.set_debug(val); +} -#define debug_writel(val) outer_cache.set_debug(val) - -static void l2x0_set_debug(unsigned long val) +static void pl310_set_debug(unsigned long val) { writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); } @@ -108,7 +107,7 @@ static inline void debug_writel(unsigned long val) { } -#define l2x0_set_debug NULL +#define pl310_set_debug NULL #endif #ifdef CONFIG_PL310_ERRATA_588369 @@ -372,6 +371,11 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) else l2x0_ways = 8; type = "L310"; +#ifdef CONFIG_PL310_ERRATA_753970 + /* Unmapped register. */ + sync_reg_offset = L2X0_DUMMY_REG; +#endif + outer_cache.set_debug = pl310_set_debug; break; case L2X0_CACHE_ID_PART_L210: l2x0_ways = (aux >> 13) & 0xf; @@ -421,7 +425,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) outer_cache.flush_all = l2x0_flush_all; outer_cache.inv_all = l2x0_inv_all; outer_cache.disable = l2x0_disable; - outer_cache.set_debug = l2x0_set_debug; printk(KERN_INFO "%s cache controller enabled\n", type); printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", |